參數(shù)資料
型號(hào)： IDT54FCT825CTSOB
廠商： Integrated Device Technology, Inc.
英文描述： CAP 0.1UF 50V 10% X7R SMD-1805 TR-7-PL SN-NIBAR
中文描述： 高性能CMOS總線接口寄存器
文件頁(yè)數(shù)： 3/9頁(yè)
文件大小： 178K
代理商： IDT54FCT825CTSOB
IDT54/74FCT821AT/BT/CT, 823/825AT/BT/CT/DT
HIGH-PERFORMANCE CMOS BUS INTERFACE REGISTERS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
6.21
3
FUNCTION TABLE
(1)
PIN DESCRIPTION
2567 tbl 01
ABSOLUTE MAXIMUM RATINGS
(1)
CAPACITANCE
(
T
A
= +25
°
C, f = 1.0MHz)
Symbol
Parameter
(1)
C
IN
Input
Capacitance
C
OUT
Output
Capacitance
Symbol
V
TERM(2)
Terminal Voltage
with Respect to
GND
V
TERM(3)
Terminal Voltage
with Respect to
GND
T
A
Operating
Temperature
T
BIAS
Temperature
Under Bias
T
STG
Storage
Temperature
P
T
Power Dissipation
Rating
Commercial
–0.5 to +7.0
Military
–0.5 to +7.0
Unit
V
–0.5 to
V
CC
+0.5
–0.5 to
V
CC
+0.5
V
0 to +70
–55 to +125
°
C
–55 to +125
–65 to +135
°
C
–55 to +125
–65 to +150
°
C
0.5
0.5
W
I
OUT
DC Output
Current
–60 to +120 –60 to +120 mA
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RAT-
INGS may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification is
not
implied. Exposure to absolute maximum rating conditions for
extended periods may affect reliability. No terminal voltage may exceed
V
CC
by +0.5V unless otherwise noted.
2. Input and V
CC
terminals only.
3. Outputs and I/O terminals only.
NOTE:
1. This parameter is measured at characterization but not tested.
2567 lnk 03
2567 lnk 04
Conditions
V
IN
= 0V
Typ.
6
Max. Unit
10
pF
V
OUT
= 0V
8
12
pF
Inputs
Internal/
Outputs
Q
I
L
H
OE
CLR
EN
D
I
L
H
CP
↑
↑
X
X
X
X
↑
↑
↑
↑
Y
I
Z
Z
Function
High Z
H
H
H
H
L
L
H
L
H
L
H
H
L
L
L
L
H
H
H
H
H
H
X
X
H
H
L
L
L
L
X
X
X
X
L
H
L
H
L
L
Z
L
Z
Clear
NC
NC
L
H
L
H
NC
Z
Z
L
H
Hold
Load
Names
D
I
CLR
I/O
I
I
Description
The D flip-flop data inputs.
When the clear input is LOW and
OE
is
LOW, the Q
I
outputs are LOW. When
the clear input is HIGH, data can be
entered into the register.
Clock Pulse for the Register; enters
data into the register on the LOW-to-
HIGH transition.
The register 3-state outputs.
Clock Enable. When the clock enable is
LOW, data on the D
I
input is transferred
to the Q
I
output on the LOW-to-HIGH
clock transition. When the clock enable
is HIGH, the Q
I
outputs do not change
state, regardless of the data or clock
input transitions.
Output Control. When the
OE
input is
HIGH, the Y
impedance state. When the
OE
input is
LOW, the TRUE register data is present
at the Y
I
outputs.
CP
I
Y
I
EN
O
I
OE
I
outputs are in the high-
NOTE:
1. H = HIGH
L = LOW
X = Don’t Care
NC = No Change
↑
= LOW-to-HIGH Transition
Z = High Impedance
2567 tbl 02
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