參數(shù)資料
型號： IDT54FCT841ADB
廠商： INTEGRATED DEVICE TECHNOLOGY INC
元件分類： 通用總線功能
英文描述： HIGH-PERFORMANCE CMOS BUS INTERFACE LATCHES
中文描述： FCT SERIES, 10-BIT DRIVER, TRUE OUTPUT, CDIP24
封裝： CERDIP-24
文件頁數(shù)： 5/7頁
文件大小： 140K
代理商： IDT54FCT841ADB
IDT54/74FCT841A/B/C
HIGH-PERFORMANCE CMOS BUS INTERFACE LATCHES
MILITARY AND COMMERCIAL TEMPERATURE RANGES
7.22
5
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
FCT841A
FCT841B
FCT841C
Com'l.
Mil.
Com'l.
Mil.
Com'l.
Mil.
Symbol
t
PLH
t
PHL
Parameter
Conditions
(1)
Min.
(2)
Max. Min.
(2)
Max. Min.
(2)
Max. Min.
(2)
Max. Min.
(2)
Max. Min.
(2)
Max.
C
L
= 50pF
R
L
= 500
C
L
= 300pF
(4)
R
L
= 500
C
L
= 50pF
R
L
= 500
C
L
= 300pF
(4)
R
L
= 500
C
L
= 50pF
1.5
12.0 1.5
14.0 1.5
R
L
= 500
1.5
14.0 1.5
17.0 1.5
1.5
13.0 1.5
14.0 1.5
Unit
Propagation Delay
D
I
to
Y
I
(LE = HIGH)
1.5
9.0
1.5
10.0 1.5
6.5
1.5
7.5
1.5
5.5
1.5
6.3
ns
1.5
13.0 1.5
15.0 1.5
13.0 1.5
15.0 1.5
13.0 1.5
15.0
t
PLH
t
PHL
Propagation Delay
LE to Y
I
1.5
12.0 1.5
13.0 1.5
8.0
1.5
10.5 1.5
6.4
1.5
6.8
ns
1.5
16.0 1.5
20.0 1.5
15.5 1.5
18.0 1.5
15.0 1.5
16.0
t
PLH
t
PHL
t
PHL
Propagation Delay,
PRE
to Y
I
8.0
10.0 1.5
10.0 1.5
1.5
10.0 1.5
13.0 1.5
11.0 1.5
7.0
9.0
9.0
1.5
1.5
1.5
9.0
12.0
10.0
ns
Propagation Delay,
CLR
to Y
I
ns
t
PLH
t
PZH
t
PZL
1.5
14.0 1.5
17.0 1.5
10.0 1.5
10.0 1.5
9.0
1.5
9.0
Output Enable Time
OE
to Y
I
C
L
= 50pF
R
L
= 500
C
L
= 300pF
(4)
R
L
= 500
C
L
= 5pF
(4)
R
L
= 500
C
L
= 50pF
R
L
= 500
C
L
= 50pF
R
L
= 500
1.5
11.5 1.5
13.0 1.5
8.0
1.5
8.5
1.5
6.5
1.5
7.3
ns
1.5
23.0 1.5
25.0 1.5
14.0 1.5
15.0 1.5
12.0 1.5
13.0
t
PHZ
t
PLZ
Output Disable Time
OE
to Y
I
1.5
7.0
1.5
9.0
1.5
6.0
1.5
6.5
1.5
5.7
1.5
6.0
ns
1.5
8.0
1.5
10.0 1.5
7.0
1.5
7.5
1.5
6.0
1.5
6.3
t
SU
Data to LE Set-up Time
2.5
—
2.5
—
2.5
—
2.5
—
2.5
—
2.5
—
ns
t
H
t
W
t
W
Data to LE Hold Time
LE Pulse Width
(3)
PRE
Pulse Width
(3)
CLR
Pulse Width
(3)
2.5
4.0
5.0
—
—
—
3.0
5.0
7.0
—
—
—
2.5
4.0
4.0
—
—
—
2.5
4.0
4.0
—
—
—
2.5
4.0
4.0
—
—
—
2.5
4.0
4.0
—
—
—
ns
ns
ns
HIGH
LOW
t
W
t
REM
t
REM
NOTES:
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. These parameters are guaranteed but not tested.
4. These conditions are guaranteed but not tested.
LOW
4.0
4.0
3.0
—
—
—
5.0
4.0
3.0
—
—
—
4.0
4.0
3.0
—
—
—
4.0
4.0
3.0
—
—
—
4.0
4.0
3.0
—
—
—
4.0
4.0
3.0
—
—
—
ns
ns
ns
Recovery Time
PRE
to LE
Recovery Time
CLR
to LE
2607 tbl 07
相關PDF資料
PDF描述
IDT54FCT841AE HIGH-PERFORMANCE CMOS BUS INTERFACE LATCHES
IDT54FCT841AEB HIGH-PERFORMANCE CMOS BUS INTERFACE LATCHES
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