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參數(shù)資料
| 型號(hào)： | IDT54FCT88915TT100J |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時(shí)鐘及定時(shí) |
| 英文描述： | LOW SKEW PLL-BASED CMOS CLOCK DRIVER (WITH 3-STATE) |
| 中文描述： | FCT SERIES, PLL BASED CLOCK DRIVER, 7 TRUE OUTPUT(S), 1 INVERTED OUTPUT(S), PQCC28 |
| 封裝： | 0.050 INCH PITCH, PLASTIC, LCC-28 |
| 文件頁(yè)數(shù)： | 6/11頁(yè) |
| 文件大?。?/td> | 140K |
| 代理商： | IDT54FCT88915TT100J |
IDT54/74FCT88915TT 55/70/100/133
LOW SKEW PLL-BASED CMOS CLOCK DRIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
9.7
6
NOTES:
7. These two specs ( t
RISE/FALL
and t
PULSE WIDTH
2Q output) guarantee that the FCT88915TT meets 68040 P-Clock input specification.
8. The wiring diagrams and written explanations of Figure 4 demonstrate the input and output frequency relationships for various possible feedback
configurations. The allowable SYNC input range to stay in the phase-locked condition is also indicated. There are two allowable SYNC frequency ranges,
depending on whether FREQ_SEL is HIGH or LOW. Also it is possible to feed back the Q5 output, thus creating a 180
°
phase shift between the SYNC
input and the Q outputs. The table below summarizes the allowable SYNC frequency range for each possible configuration.
9. The tPD spec describes how the phase offset between the SYNC input and the output connected to the FEEDBACK input, varies with process, temperature
and voltage. Measurements were made with a 10MHz SYNC input and Q/2 output as feedback. The phase measurements were made at 1.5V.
The Q/2 output was terminated at the FEEDBACK input with 100
to V
CC
and 100
to ground.
tPD measurements were made with the loop filter connection shown below:
LF
External Loop
Filter
0.1
μ
F
C1
Analog GND
3072 tbl 09
3072 drw 05
3072 drw 04
68040
P-Clock
Input
88915TT
2Q
Output
Rp
Zo (clock trace)
Rp = 1.5 Zo
FREQ_SEL
Level
HIGH
Feedback
Output
Q/2
Allowable SYNC Input
Frequency Range (MH
Z
)
10 to (2Q f
MAX
Spec)/4
Corresponding 2Q output
Frequency Range
40 to (2Q f
MAX
Spec)
Phase Relationship
of the Q Outputs
to Rising SYNC Edge
0
°
HIGH
Any Q (Q0-Q4)
20 to (2Q f
MAX
Spec)/2
40 to (2Q f
MAX
Spec)
0
°
HIGH
Q5
20 to (2Q f
MAX
Spec)/2
40 to (2Q f
MAX
Spec)
180
°
HIGH
2Q
40 to (2Q f
MAX
Spec)
40 to (2Q f
MAX
Spec)
0
°
LOW
Q/2
5 to (2Q f
MAX
Spec)/8
20 to (2Q f
MAX
Spec)/2
0
°
LOW
Any Q (Q0-Q4)
10 to (2Q f
MAX
Spec)/4
20 to (2Q f
MAX
Spec)/2
0
°
LOW
Q5
10 to (2Q f
MAX
Spec)/4
20 to (2Q f
MAX
Spec)/2
180
°
LOW
2Q
20 to (2Q f
MAX
Spec)/2
20 to (2Q f
MAX
Spec)/2
0
°
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| IDT54FCT88915TT100JB | LOW SKEW PLL-BASED CMOS CLOCK DRIVER (WITH 3-STATE) |
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