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參數(shù)資料
| 型號(hào)： | IDT54FCT88915TT100L |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時(shí)鐘及定時(shí) |
| 英文描述： | LOW SKEW PLL-BASED CMOS CLOCK DRIVER (WITH 3-STATE) |
| 中文描述： | FCT SERIES, PLL BASED CLOCK DRIVER, 7 TRUE OUTPUT(S), 1 INVERTED OUTPUT(S), CQCC28 |
| 封裝： | LCC-28 |
| 文件頁數(shù)： | 2/11頁 |
| 文件大?。?/td> | 140K |
| 代理商： | IDT54FCT88915TT100L |
IDT54/74FCT88915TT 55/70/100/133
LOW SKEW PLL-BASED CMOS CLOCK DRIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
9.7
2
PIN CONFIGURATIONS
PIN DESCRIPTION
3072 tbl 01
Pin Name
SYNC(0)
SYNC(1)
REF_SEL
I/O
I
I
I
Description
Reference clock input.
Reference clock input.
Chooses reference between SYNC (0) & SYNC (1). (Refer to functional block diagram).
Selects between
÷
1 and
÷
2 frequency options. (Refer to functional block diagram).
Feedback input to phase detector.
Input for external loop filter connection.
FREQ_SEL
FEEDBACK
LF
I
I
I
Q0-Q4
Q5
O
O
O
O
Clock output.
Inverted clock output.
Clock output (2 x Q frequency).
Clock output (Q frequency
÷
2).
Indicates phase lock has been achieved (HIGH when locked).
Asynchronous reset (active LOW) and output enable (active HIGH). When HIGH, outputs are
enabled. When LOW, outputs are in HIGH impedance.
Disables phase-lock for low frequency testing. (Refer to functional block diagram).
2Q
Q/2
LOCK
OE/RST
O
I
PLL_EN
I
Q/2
GND
Q3
V
CC
Q2
GND
LOCK
25
24
23
22
21
20
19
FEEDBK
REF_SEL
SYNC(0)
V
CC
LF
GND(AN)
SYNC(1)
5
6
7
8
9
10
11
P
G
Q
V
C
Q
G
F
12
13
14
15
16
17
18
J28-1,
L28-1
O
V
C
Q
G
Q
V
C
2
28
4
3
2
1
27
26
3072 drw 02
5
6
7
8
9
10
11
V
CC
OE/RST
FEEDBACK
REF_SEL
SYNC(0)
V
CC
(AN)
1
2
3
4
20
19
18
17
16
15
14
13
Q4
V
CC
2Q
12
GND
Q5
Q/2
GND
Q3
V
CC
LF
Q2
GND
LOCK
GND(AN)
SO28-7
21
22
23
24
SYNC(1)
FREQ_SEL
GND
Q0
V
CC
Q1
GND
PLL_EN
25
26
27
28
3072 drw 03
SSOP
TOP VIEW
PLCC/LCC
TOP VIEW
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| IDT54FCT88915TT100LB | LOW SKEW PLL-BASED CMOS CLOCK DRIVER (WITH 3-STATE) |
| IDT54FCT88915TT100PY | LOW SKEW PLL-BASED CMOS CLOCK DRIVER (WITH 3-STATE) |
| IDT54FCT88915TT100PYB | LOW SKEW PLL-BASED CMOS CLOCK DRIVER (WITH 3-STATE) |
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| IDT54FCT88915TT133J | LOW SKEW PLL-BASED CMOS CLOCK DRIVER (WITH 3-STATE) |
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