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參數(shù)資料
| 型號(hào)： | IDT54FCT88915TT133 |
| 廠(chǎng)商： | Integrated Device Technology, Inc. |
| 英文描述： | LOW SKEW PLL-BASED CMOS CLOCK DRIVER (WITH 3-STATE) |
| 中文描述： | 低歪曲基于PLL的CMOS時(shí)鐘驅(qū)動(dòng)器（具有三態(tài)） |
| 文件頁(yè)數(shù)： | 7/11頁(yè) |
| 文件大小： | 140K |
| 代理商： | IDT54FCT88915TT133 |
IDT54/74FCT88915TT 55/70/100/133
LOW SKEW PLL-BASED CLOCK DRIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
9.7
7
NOTES:
1. Figure 1 shows a loop filter and analog isolation scheme which will be effective in most applications. The following guidelines should be followed to ensure
stable and jitter-free operation:
a.
All loop filter and analog isolation components should be tied as close to the package as possible. Stray current passing through the parasitics of
long traces can cause undesirable voltage transients at the LF pin.
The 10
μ
F low frequency bypass capacitor and the 0.1
μ
F high frequency bypass capacitor form a wide bandwidth filter that will minimize the
88915TT's sensitivity to voltage transients from the system digital V
CC
supply and ground planes.
If good bypass techniques are used on a board design near components which may cause digital V
CC
and ground noise, V
CC
step deviations should
not occur at the 88915TT's digital V
CC
supply. The purpose of the bypass filtering scheme shown in figure 1 is to give the 88915TT additional
protection from the power supply and ground plane transients that can occur in a high frequency, high speed digital system.
The loop filter capacitor (0.1
μ
F) can be a ceramic chip capacitor, the same as a standard bypass capacitor.
2. In addition to the bypass capacitors used in the analog filter of figure 1 there should be a 0.1
μ
F bypass capacitor between each of the other (digital) four
V
CC
pins and the board ground plane. This will reduce output switching noise caused by the 88915TT outputs, in addition to reducing potential for noise
in the "analog" section of the chip. These bypass capacitors should also be tied as close to the 88915TT package as possible.
b.
c.
BOARD V
CC
0.1
μ
F (Loop
Filter Cap)
Analog loop filter
section of the
FCT88915TT
0.1
μ
F
High
Freq.
Bypass
10
μ
F
Low
Freq.
Bypass
BOARD GND
A separate Analog power supply is not necessary
and should not be used. Following these prescribed
guidelines is all that is necessary to use the
FCT88915TT in a normal digital environment.
ANALOG V
CC
ANALOG GND
LF
3072 drw 06
Figure 1. Recommended Loop Filter and Analog Isolation Scheme for the FCT88915TT
相關(guān)PDF資料 |
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| IDT54FCT88915TT133J | LOW SKEW PLL-BASED CMOS CLOCK DRIVER (WITH 3-STATE) |
| IDT54FCT88915TT133JB | LOW SKEW PLL-BASED CMOS CLOCK DRIVER (WITH 3-STATE) |
| IDT54FCT88915TT133L | LOW SKEW PLL-BASED CMOS CLOCK DRIVER (WITH 3-STATE) |
| IDT54FCT88915TT133LB | LOW SKEW PLL-BASED CMOS CLOCK DRIVER (WITH 3-STATE) |
| IDT54FCT88915TT133PY | LOW SKEW PLL-BASED CMOS CLOCK DRIVER (WITH 3-STATE) |
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