- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄377238 > IDT54FCT88915TT133JB (INTEGRATED DEVICE TECHNOLOGY INC) LOW SKEW PLL-BASED CMOS CLOCK DRIVER (WITH 3-STATE) PDF資料下載
參數(shù)資料
| 型號： | IDT54FCT88915TT133JB |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時鐘及定時 |
| 英文描述： | LOW SKEW PLL-BASED CMOS CLOCK DRIVER (WITH 3-STATE) |
| 中文描述： | FCT SERIES, PLL BASED CLOCK DRIVER, 7 TRUE OUTPUT(S), 1 INVERTED OUTPUT(S), PQCC28 |
| 封裝： | 0.050 INCH PITCH, PLASTIC, LCC-28 |
| 文件頁數(shù)： | 10/11頁 |
| 文件大小： | 140K |
| 代理商： | IDT54FCT88915TT133JB |
IDT54/74FCT88915TT 55/70/100/133
LOW SKEW PLL-BASED CMOS CLOCK DRIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
9.7
10
TEST CIRCUITS AND WAVEFORM
50
to V
CC
/2, C
L
= 20pF
PROPAGATION DELAY, OUTPUT SKEW
ENABLE AND DISABLE TEST CIRCUIT
Pulse
Generator
R
T
D.U.T.
V
CC
V
IN
C
L
V
OUT
50pF
500
500
7.0V
NOTES:
1. Diagram shown for input Control Enable-LOW and input Control Disable-
HIGH
2. Pulse Generator for All Pulses: t
F
≤
2.5ns; t
R
≤
2.5ns
3072 lnk 12
Pulse
Generator
R
T
D.U.T.
V
CC
V
IN
V
OUT
100
100
V
CC
20pF
3072 drw 11
NOTES:
1. The FCT88915TT aligns rising edges of the FEEDBACK input and SYNC input, therefore the SYNC input does not require a 50% duty cycle.
2. All skew specs are measured between the 1.5V crossing point of the appropriate output edges. All skews are specified as "windows", not as
±
deviation
around a center point.
3. If a Q output is connected to the FEEDBACK input (this situation is not shown), the Q output frequency would match the SYNC input frequency, the 2Q
output would run at twice the SYNC frequency and the Q/2 output would run at half the SYNC frequency.
ENABLE AND DISABLE TIMES
(These waveforms represent the hookup of Figure 2a)
t
t
t
t
t
PD
SYNC INPUT
(SYNC (1) or
SYNC (0))
FEEDBACK
INPUT
Q/2 OUTPUT
Q
0
-Q
4
OUTPUTS
Q5 OUTPUT
2Q OUTPUT
tSKEWALL
SKEWf
SKEWr
SKEWf
SKEWr
t
"Q" OUTPUTS
CYCLE
1.5V
1.5V
1.5V
1.5V
1.5V
1.5V
3072 drw 13
t
CYCLE SYNC INPUT
Test
Switch
Closed
Disable Low
Enable Low
Disable High
Enable High
Open
DEFINITIONS:
C
L
=
Load capacitance: includes jig and probe capacitance.
R
T
=
Termination resistance: should be equal to Z
OUT
of the Pulse
Generator.
3072 tbl 10
CONTROL
INPUT
3V
1.5V
0V
3.5V
0V
OUTPUT
NORMALLY
LOW
OUTPUT
NORMALLY
HIGH
SWITCH
CLOSED
SWITCH
OPEN
V
OL
V
OH
0.3V
0.3V
t
PLZ
t
PZL
t
PZH
t
PHZ
0V
1.5V
1.5V
ENABLE
DISABLE
SWITCH POSITION
3072 drw 14
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| IDT54FCT88915TT133L | LOW SKEW PLL-BASED CMOS CLOCK DRIVER (WITH 3-STATE) |
| IDT54FCT88915TT133LB | LOW SKEW PLL-BASED CMOS CLOCK DRIVER (WITH 3-STATE) |
| IDT54FCT88915TT133PY | LOW SKEW PLL-BASED CMOS CLOCK DRIVER (WITH 3-STATE) |
| IDT54FCT88915TT133PYB | LOW SKEW PLL-BASED CMOS CLOCK DRIVER (WITH 3-STATE) |
| IDT54FCT88915TT70 | LOW SKEW PLL-BASED CMOS CLOCK DRIVER (WITH 3-STATE) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IDT557GI-05ALF | 制造商: 功能描述: 制造商:undefined 功能描述: |
| IDT557GI-06LF | 制造商: 功能描述: 制造商:undefined 功能描述: |
| IDT5962-8855201XA | 制造商:Integrated Device Technology Inc 功能描述: |
| IDT5991A-2J | 制造商:Integrated Device Technology Inc 功能描述:EIGHT DISTRIBUTED-OUTPUT CLOCK DRIVER, 32 Pin, Plastic, PLCC |
| IDT5991A-2JG | 功能描述:IC CLK DVR PLL FANOUT 32-PLCC RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:TurboClock™ 標(biāo)準(zhǔn)包裝:1,000 系列:- 類型:時鐘/頻率合成器，扇出分配 PLL:- 輸入:- 輸出:- 電路數(shù):- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 除法器/乘法器:- 電源電壓:- 工作溫度:- 安裝類型:表面貼裝 封裝/外殼:56-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:56-VFQFP-EP（8x8） 包裝:帶卷 (TR) 其它名稱:844S012AKI-01LFT |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。