參數(shù)資料
型號: IDT54FCT88915TT133PYB
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: 時鐘及定時
英文描述: LOW SKEW PLL-BASED CMOS CLOCK DRIVER (WITH 3-STATE)
中文描述: FCT SERIES, PLL BASED CLOCK DRIVER, 7 TRUE OUTPUT(S), 1 INVERTED OUTPUT(S), PDSO28
封裝: 5.30 MM, 0.65 MM PITCH, SSOP-28
文件頁數(shù): 4/11頁
文件大?。?/td> 140K
代理商: IDT54FCT88915TT133PYB
IDT54/74FCT88915TT 55/70/100/133
LOW SKEW PLL-BASED CMOS CLOCK DRIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
9.7
4
POWER SUPPLY CHARACTERISTICS
OUTPUT FREQUENCY SPECIFICATIONS
NOTES:
1. Note 8 in "General AC Specification Notes" and Figure 2 describes this specification and its actual limits depending on the feedback connection.
2. Maximum operating frequency is guaranteed with the part in a phase locked condition and all outputs loaded.
SYNC INPUT TIMING REQUIREMENTS
Symbol
Parameter
T
RISE/FALL
Rise/Fall Times,
SYNC inputs
(0.8V to 2.0V)
Frequency Input Frequency,
SYNC Inputs
Duty Cycle Input Duty Cycle,
SYNC Inputs
3053 tbl 06
3072 tbl 07
Min.
Max.
3.0
Unit
ns
10
(1)
2Q fmax
MHz
25%
75%
Max.
(2)
70
70
Symbol
f2Q
Parameter
Min.
40
55
55
100
100
133
133
Unit
MHz
Operating frequency 2Q Output
Operating frequency Q0-Q4, Q5 Outputs
fQ
fQ/2
20
10
27.5
13.75
35
17.5
50
25
66.7
33.3
MHz
MHz
Operating frequency Q/2 Output
Symbol
I
CC
Parameter
Test Conditions
(1)
Min.
Typ.
(2)
0.5
Max.
1.5
Unit
mA
Quiescent Power Supply Current
TTL Inputs HIGH
Dynamic Power Supply
Current
(4)
V
CC
= Max.
V
IN
= V
CC
–2.1V
(3)
V
CC
= Max.
All Outputs Open
I
CCD
V
IN
= V
CC
V
IN
= GND
0.25
0.4
mA/
MHz
C
PD
I
C
Power Dissipation Capacitance
Total Power Supply Current
(5,6)
50% Duty Cycle
V
CC
= Max.
PLL_EN = 1, LOCK = 1, FEEDBACK = Q/2
SYNC frequency = 20MHz. Q/2 loaded with 50pF
All other outputs open
15
25
40
40
pF
mA
V
CC
= Max.
PLL_EN = 1, LOCK = 1, FEEDBACK = Q/2
SYNC frequency = 20MHz. Q/2 loaded with 50
Thevenin termination. All other outputs open
42
60
mA
NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics.
2. Typical values are at V
CC
= 5.0V, +25
°
C ambient.
3. Per TTL driven input; all other inputs at V
CC
or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations. It is derived with Q frequency as the reference.
5. Values for these conditions are examples of the I
CC
formula. These limits are guaranteed but not tested.
6. I
C
= I
QUIESCENT
+ I
INPUTS
+ I
DYNAMIC
I
C
= I
CC
+
I
CC
D
H
N
T
+ I
CCD
(f) + I
LOAD
I
CC
= Quiescent Current (I
CCL
,
I
CCH
and I
CCZ
)
I
CC
= Power Supply Current for a TTL High Input
D
H
= Duty Cycle for TTL Inputs High
N
T
= Number of TTL Inputs at D
H
I
CCD
= Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
f = 2Q frequency
I
LOAD
= Dynamic Current due to load.
3072 tbl 05
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IDT54FCT88915TT70 LOW SKEW PLL-BASED CMOS CLOCK DRIVER (WITH 3-STATE)
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