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參數(shù)資料
| 型號(hào)： | IDT5992A-7JI |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時(shí)鐘及定時(shí) |
| 英文描述： | PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQCC32 |
| 封裝： | PLASTIC, LCC-32 |
| 文件頁數(shù)： | 5/8頁 |
| 文件大?。?/td> | 67K |
| 代理商： | IDT5992A-7JI |
5
COMMERCIALANDINDUSTRIALTEMPERATURERANGES
IDT5992A
PROGRAMMABLESKEWPLLCLOCKDRIVERTURBOCLOCK
INPUT TIMING REQUIREMENTS
Symbol
Description(1)
Min.
Max.
Unit
tR, tF
Maximum input rise and fall times, 0.8V to 2V
—
10
ns/V
tPWC
Input clock pulse, HIGH or LOW
3
—
ns
DH
Input duty cycle
10
90
%
REF
ReferenceClockInput
3.75
100
MHz
NOTE:
1. Where pulse width implied by DH is less than tPWC limit, tPWC limit applies.
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
IDT5992A-2
IDT5992A-5
IDT5992A-7
Symbol Parameter
Min.
Typ.
Max.
Min.
Typ.
Max.
Min.
Typ.
Max.
Unit
FNOM
VCO Frequency Range
SeePLLProgrammableSkewRangeandResolutionTable
tRPWH
REF Pulse Width HIGH(1)
3—
—
3
—
3
—
ns
tRPWL
REF Pulse Width LOW(1)
3—
—
3
—
3
—
ns
tU
ProgrammableSkewTimeUnit
SeeControlSummaryTable
tSKEWPR Zero Output Matched-Pair Skew (xQ0, xQ1)(1,2,3)
—
0.05
0.2
—
0.1
0.25
—
0.1
0.25
ns
tSKEW0
Zero Output Skew (All Outputs)(1,4,5)
—
0.1
0.25
—
0.25
0.5
—
0.3
0.75
ns
tSKEW1
Output Skew
—
0.25
0.5
—
0.6
0.7
—
0.6
1
ns
(Rise-Rise, Fall-Fall, Same Class Outputs)(1,3)
tSKEW2
Output Skew
—
0.5
1.2
—
0.6
1.5
—
0.5
1.5
ns
(Rise-Fall,Nominal-Inverted,Divided-Divided)(1,6)
tSKEW3
Output Skew
—
0.25
0.5
—
0.5
0.7
—
0.7
1.2
ns
(Rise-Rise,Fall-Fall,DifferentClassOutputs)(1,6)
tSKEW4
Output Skew
—
0.5
0.9
—
0.6
1.7
—
1.2
1.7
ns
(Rise-Fall,Nominal-Divided,Divided-Inverted)(1,2)
tDEV
Device-to-Device Skew(1,2,7)
—
0.75
—
1.25
—
1.65
ns
tPD
REF Input to FB Propagation Delay(1,9)
0.25
0
0.25
0.5
0
0.5
0.7
0
0.7
ns
tODCV
Output Duty Cycle Variation from 50%(1)
0.5
0
0.5
1.2
0
1.2
1.5
0
1.5
ns
tPWH
Output HIGH Time Deviation from 50%(1,10)
—
3
—
4
—
5.5
ns
tPWL
Output LOW Time Deviation from 50%(1,11)
—
3
—
4
—
5.5
ns
tORISE
OutputRiseTime(1)
0.5
2
2.5
0.5
2
3.5
0.5
3
5
ns
tOFALL
OutputFallTime(1)
0.5
2
2.5
0.5
2
3.5
0.5
3
5
ns
tLOCK
PLL Lock Time(8)
—
0.5
—
0.5
—
0.5
ms
tJR
Cycle-to-CycleOutputJitter(1)
RMS
—
25
—
25
—
25
ps
Peak-to-Peak
—
200
—
200
—
200
NOTES:
1. All timing and jitter tolerances apply for FNOM > 25MHz.
2. Skew is the time between the earliest and the latest output transition among all outputs for which the same tU delay has been selected when all are loaded with the specified
load.
3. tSKEWPR is the skew between a pair of outputs (xQ0 and xQ1) when all eight outputs are selected for 0tU.
4. tSKEW0 is the skew between outputs when they are selected for 0tU.
5. For IDT5992A-2 tSKEW0 is measured with CL = 0pF; for CL = 30pF, tSKEW0 = 0.45ns Max.
6. There are 3 classes of outputs: Nominal (multiple of tU delay), Inverted (4Q0 and 4Q1 only with 4F0 = 4F1 = HIGH), and Divided (3Qx and 4Qx only in Divide-by-2 or Divide-
by-4 mode).
7. tDEV is the output-to-output skew between any two devices operating under the same conditions (VDD ambient temperature, air flow, etc.)
8. tLOCK is the time that is required before synchronization is achieved. This specification is valid only after VDD is stable and within normal operating limits. This parameter is
measured from the application of a new signal or frequency at REF or FB until tPD is within specified limits.
9. tPD is measured with REF input rise and fall times (from 0.2VDD to 0.8VDD ) of 1.5ns.
10. Measured at 0.8VDD.
11. Measured at 0.2VDD.
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