參數(shù)資料
型號(hào)： IDT5T2010BBI8
廠商： INTEGRATED DEVICE TECHNOLOGY INC
元件分類： 時(shí)鐘及定時(shí)
英文描述： 5T SERIES, PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PBGA144
封裝： PLASTIC, BGA-144
文件頁數(shù)： 5/24頁
文件大小： 201K
代理商： IDT5T2010BBI8
13
INDUSTRIALTEMPERATURERANGE
IDT5T2010
2.5V ZERO DELAY PLL CLOCK DRIVER TERACLOCK
SINGLE-ENDED INPUT AC TEST CONDITIONS FOR 2.5V LVTTL
Symbol
Parameter
Value
Units
VIH
Input HIGH Voltage
VDD
V
VIL
Input LOW Voltage
0V
VTHI
Input Timing Measurement Reference Level(1)
VDD/2
V
tR, tF
Input Signal Edge Rate(2)
2
V/ns
NOTES:
1. A nominal 1.25V timing measurement reference level is specified to allow constant, repeatable results in an automatic test equipment (ATE) environment.
2. The input signal edge rate of 2V/ns or greater is to be maintained in the 10% to 90% range of the input waveform.
DIFFERENTIAL INPUT AC TEST CONDITIONS FOR 2.5V LVTTL
Symbol
Parameter
Value
Units
VDIF
Input Signal Swing(1)
VDD
V
VX
Differential Input Signal Crossing Point(2)
VDD/2
V
VTHI
Input Timing Measurement Reference Level(3)
Crossing Point
V
tR, tF
Input Signal Edge Rate(4)
2.5
V/ns
NOTES:
1. A nominal 2.5V peak-to-peak input pulse level is specified to allow consistent, repeatable results in an automatic test equipment (ATE) environment. This device meets the VDIF
(AC) specification under actual use conditions.
2. A nominal 1.25V crossing point level is specified to allow consistent, repeatable results in an automatic test equipment (ATE) environment. This device meets the VX specification
under actual use conditions.
3. In all cases, input waveform timing is marked at the differential cross-point of the input signals.
4. The input signal edge rate of 2.5V/ns or greater is to be maintained in the 20% to 80% range of the input waveform.
POWER SUPPLY CHARACTERISTICS FOR 2.5V LVTTL OUTPUTS(1)
Symbol
Parameter
Test Conditions(2)
Typ.
Max
Unit
IDDQ
Quiescent VDD Power Supply Current(3)
VDDQ = Max., REF = LOW,
PD = HIGH, nSOE = LOW,
15
25
mA
PLL_EN = HIGH, DS[1:0] = MM, nF[2:1] = LH,
FBF[2:1] = LH, Outputs enabled, All outputs unloaded
IDDQQ
Quiescent VDDQ Power Supply Current(3)
VDDQ = Max., REF = LOW,
PD = HIGH, nSOE = LOW,
12
50
μA
PLL_EN = HIGH, DS[1:0] = MM, nF[2:1] = LH,
FBF[2:1] = LH, Outputs enabled, All outputs unloaded
IDDPD
Power Down Current
VDD = Max.,
PD = LOW, nSOE = LOW, PLL_EN = HIGH
0.5
3
mA
IDDD
Dynamic VDD Power Supply
VDD = Max., VDDQ = Max., CL = 0pF
15
25
μA/MHz
CurrentperOutput
IDDDQ
Dynamic VDDQ Power Supply
VDD = Max., VDDQ = Max., CL = 0pF
30
40
μA/MHz
CurrentperOutput
ITOT
Total Power VDD Supply Current(4)
VDDQ = 2.5V., FVCO = 100MHz, CL = 15pF
40
60
mA
VDDQ = 2.5V., FVCO = 250MHz, CL = 15pF
60
90
ITOTQ
Total Power VDDQ Supply Current(4)
VDDQ = 2.5V., FVCO = 100MHz, CL = 15pF
80
120
mA
VDDQ = 2.5V., FVCO = 250MHz, CL = 15pF
200
300
NOTES:
1. These power consumption characteristics are for all the valid input interfaces and cover the worst case input and output interface combinations.
2. The termination resistors are excluded from these measurements.
3. If the differential input interface is used, the true input is held LOW and the complementary input is held HIGH.
4. FS = HIGH.
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