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參數(shù)資料
| 型號： | IDT5T9950APFGI8 |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時鐘及定時 |
| 英文描述： | 5T SERIES, PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32 |
| 封裝： | LEAD FREE, TQFP-32 |
| 文件頁數(shù)： | 3/9頁 |
| 文件大?。?/td> | 81K |
| 代理商： | IDT5T9950APFGI8 |
3
INDUSTRIALTEMPERATURERANGE
IDT5T9950/A
2.5V PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK II JR.
Output skew with respect to the REF input is adjustable to compensate
for PCB trace delays, backplane propagation delays or to accommodate
requirements for special timing relationships between clocked compo-
nents. Skew is selectable as a multiple of a time unit (tU) which ranges
from 782ps to 1.5625ns for Standard version and 6.25ps to 1.3ns for A
version (see Programmable Skew Range and Resolution Table). There
are nine skew configurations available for each output pair. These con-
figurations are chosen by the nF1:0 control pins. In order to minimize the
number of control pins, 3-level inputs (HIGH-MID-LOW) are used, they
are intended for but not restricted to hard-wiring. Undriven 3-level in-
puts default to the MID level. Where programmable skew is not a re-
quirement, the control pins can be left open for the zero skew default
setting. The Control Summary Table shows how to select specific skew
taps by using the nF1:0 control pins.
PROGRAMMABLESKEW
EXTERNALFEEDBACK
By providing external feedback, the IDT5T9950 gives users flexibility
with regard to skew adjustment. The FB signal is compared with the
input REF signal at the phase detector in order to drive the VCO. Phase
differences cause the VCO of the PLL to adjust upwards or downwards
accordingly.
NOTES:
1. The device may be operated outside recommended frequency ranges without damage, but functional operation is not guaranteed.
2. The level to be set on FS is determined by the nominal operating frequency of the VCO and Time Unit Generator. The VCO frequency always appears at 1Q1:0, 2Q1:0, and
the higher outputs when they are operated in their undivided modes. The frequency appearing at the REF and FB inputs will be the same as the VCO when the output connected
to FB is undivided. The frequency of the REF and FB inputs will be 1/2 or 1/4 the VCO frequency when the part is configured for frequency multiplication by using a divided
output as the FB input.
3. Skew adjustment range assumes that a zero skew output is used for feedback. If a skewed Q output is used for feedback, then adjustment range will be greater. For example
if a 4tU skewed output is used for feedback, all other outputs will be skewed –4tU in addition to whatever skew value is programmed for those outputs. ‘Max adjustment’ range
applies to output pairs 3 and 4 where ± 6tU skew adjustment is possible and at the lowest FNOM value.
An internal loop filter moderates the response of the VCO to the
phase detector. The loop filter transfer function has been chosen to
provide minimal jitter (or frequency variation) while still providing accu-
rate responses to input frequency changes.
IDT5T9950
IDT5T9950A
FS = LOW
FS = MID
FS = HIGH
FS = LOW
FS = MID
FS = HIGH
Comments
Timing Unit Calculation (tU)
1/(32 x FNOM)
1/(16 x FNOM)
1/(8 x FNOM)
1/(32 x FNOM) 1/(16 x FNOM)
1/(8 x FNOM)
VCO Frequency Range (FNOM)(1,2)
24 to 40MHz
40 to 80MHz
80 to 160MHz
24 to 50MHz
48 to 100MHz
96 to 200MHz
Skew Adjustment Range(3)
Max Adjustment:
±7.8125ns
±9.375ns
±7.8125ns
ns
±67.5°
±135°
±270°
±67.5°
±135°
±270°
Phase Degrees
±18.75%
±37.5%
±75%
±18.75%
±37.5%
±75%
% of Cycle Time
Example 1, FNOM = 25MHz
tU = 1.25ns
—
tU = 1.25ns
—
Example 2, FNOM = 37.5MHz
tU = 0.833ns
—
tU = 0.833ns
—
Example 3, FNOM = 50MHz
—
tU = 1.25ns
—
tU = 0.625ns
tU = 1.25ns
—
Example 4, FNOM = 75MHz
—
tU = 0.833ns
—
tU = 0.833ns
—
Example 5, FNOM = 100MHz
—
tU = 1.25ns
—
tU = 0.625ns
tU = 1.25ns
Example 6, FNOM = 150MHz
—
tU = 0.833ns
—
tU = 0.833ns
Example 7, FNOM = 200MHz
—
tU = 0.625ns
PROGRAMMABLE SKEW RANGE AND RESOLUTION TABLE
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