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參數(shù)資料
| 型號： | IDT5T995PFGI |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時鐘及定時 |
| 英文描述： | 5T SERIES, PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP44 |
| 封裝： | GREEN, TQFP-44 |
| 文件頁數(shù)： | 3/10頁 |
| 文件大?。?/td> | 120K |
| 代理商： | IDT5T995PFGI |
2
INDUSTRIALTEMPERATURERANGE
IDT5T995/A
2.5V PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK II
PIN CONFIGURATION
NOTE:
1. Stresses beyond those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions above those indicated in the
operational sections of this specification is not implied. Exposure to absolute-
maximum-rated conditions for extended periods may affect device reliability.
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
Description
Max
Unit
VDDQ, VDD
Supply Voltage to Ground
–0.5 to +4.6
V
VI
DC Input Voltage
–0.5 to VDD+0.5
V
REF Input Voltage
–0.5 to +4.6
V
Maximum Power
TA = 85°C
0.7
W
Dissipation
TA = 55°C
1.1
TSTG
Storage Temperature Range
–65 to +150
°C
NOTE:
1. Capacitance applies to all inputs except TEST, FS, nF[1:0], and DS[1:0].
CAPACITANCE(TA=+25°C,f=1MHz,VIN=0V)
Parameter
Description
Typ.
Max.
Unit
CIN
InputCapacitance
5
7
pF
TQFP
TOP VIEW
NOTE:
1. When TEST = MID and sOE = HIGH, PLL remains active with nF[1:0] = LL functioning as an output disable control for individual output banks. Skew selections remain in
effect unless nF[1:0] = LL.
PIN DESCRIPTION
Pin Name
Type
Description
REF
IN
ReferenceClockInput
FB
IN
FeedbackInput
TEST(1)
IN
When MID or HIGH, disables PLL (except for conditions of Note 1). REF goes to all outputs. Skew Selections (See Control Summary
Table)remainineffect. SetLOWfornormaloperation.
sOE(1)
IN
Synchronous Output Enable. When HIGH, it stops clock outputs (except 2Q0 and 2Q1) in a LOW state (for PE = H) - 2Q0 and 2Q1may
be used as the feedback signal to maintain phase lock. When TEST is held at MID level and sOE is HIGH, the nF[1:0]pinsactasoutput
disable controls for individual banks when nF[1:0] = LL. Set sOE LOW for normal operation (has internal pull-down).
PE
IN
Selectablepositiveornegativeedgecontrol. WhenLOW/HIGHtheoutputsaresynchronizedwiththenegative/positiveedgeofthereference
clock(hasinternalpull-up).
nF[1:0]
IN
3-level inputs for selecting 1 of 9 skew taps or frequency functions
FS
IN
Selectsappropriateoscillatorcircuitbasedonanticipatedfrequencyrange. (SeeProgrammableSkewRange.)
nQ[1:0]
OUT
Fourbanksoftwooutputswithprogrammableskew
DS[1:0]
IN
3-levelinputsforfeedbackdividerselection
PD
IN
Power down control. Shuts off entire chip when LOW (has internal pull-up).
LOCK
OUT
PLL lock indication signal. HIGH indicates lock. LOW indicates that the PLL is not locked and outputs may not be synchronized to the
inputs. (For more information on application specific use of the LOCK pin, please see AN237.)
VDDQ
PWR
Powersupplyforoutputbuffers
VDD
PWR
Powersupplyforphaselockedloop,lockoutput,andotherinternalcircuitry
GND
PWR
Ground
4F1
sOE
PE
VDDQ
4Q1
4Q0
GND
PD
VDDQ
GND
1
2
3
4
5
6
7
8
9
10
11
12 13 14 15 16 17 18 19 20 21 22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
1F0
VDDQ
1Q0
1Q1
GND
DS1
DS0
VDDQ
GND
LOCK
3
F
0
F
S
V
D
R
E
F
G
N
D
T
E
S
T
2
F
1
2
F
0
4
F
0
3
F
1
F
1
G
N
D
3
Q
1
3
Q
0
V
D
Q
F
B
V
D
Q
2
Q
1
2
Q
0
V
D
Q
V
D
Q
G
N
D
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