參數(shù)資料
型號: IDT5V19EE604NDGI8
廠商: IDT, Integrated Device Technology Inc
文件頁數(shù): 20/29頁
文件大?。?/td> 0K
描述: IC PLL CLK GEN 200MHZ 28VFQFPN
特色產(chǎn)品: VersaClock III Timing Devices
標(biāo)準(zhǔn)包裝: 2,500
系列: VersaClock™ III
類型: 時鐘發(fā)生器,多路復(fù)用器
PLL: 帶旁路
輸入: LVCMOS,LVTTL,晶體
輸出: LVCMOS,LVTTL
電路數(shù): 1
比率 - 輸入:輸出: 2:6
差分 - 輸入:輸出: 無/無
頻率 - 最大: 200MHz
除法器/乘法器: 是/是
電源電壓: 3.135 V ~ 3.465 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 28-VFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝: 28-VFQFPN(4x4)
包裝: 帶卷 (TR)
IDT5V19EE604
EEPROM PROGRAMMABLE VCXO CLOCK GENERATOR
CLOCK SYNTHESIZER
IDT EEPROM PROGRAMMABLE VCXO CLOCK GENERATOR
27
IDT5V19EE604
REV M 092412
Package Outline and Package Dimensions (28-pin 4mm x 4mm QFN)
Package dimensions are kept current with JEDEC Publication No. 95
Ordering Information
“G” after the two-letter package code are the Pb-Free configuration and are RoHS compliant.
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes
no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No
other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications
such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not
recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT
does not authorize or warrant any IDT product for use in life support devices or critical medical instruments.
Millimeters
Symbol
Min
Max
A0.80
1.00
A1
0
0.05
A3
0.20 Reference
b0.15
0.25
e
0.40 BASIC
N28
ND
7
NE
7
D x E BASIC
4.00 x 4.00
D2
2.50
2.70
E2
2.50
2.70
L0.30
0.50
Part / Order Number
Marking
Shipping Packaging
Package
Temperature
5V19EE604NDGI
See Page 26
Trays
28-pin QFN
-40 to +85
° C
5V19EE604NDGI8
See Page 26
Tape and Reel
28-pin QFN
-40 to +85
° C
Sawn
Singulation
1
2
N
E
D
Index Area
Top View
Seating Plane
A3
A1
C
A
L
E2
2
D2
2
e
C
0.08
(Ref)
N
D & NE
Odd
(Ref)
N
D & NE
Even
(N
D-1)x
(Ref)
e
N
1
2
b
Thermal Base
(Typ)
If N
D & NE
are Even
(N
E-1)x
(Ref)
e
2
EP – exposed thermal
pad should be externally
connected to GND
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