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參數(shù)資料
| 型號(hào)： | IDT5V41066PGGI |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數(shù)： | 10/14頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CLOCK SYNTHESIZER 20TSSOP |
| 產(chǎn)品培訓(xùn)模塊： | Timing Solutions for PCI-Express |
| 標(biāo)準(zhǔn)包裝： | 74 |
| 類型： | 時(shí)鐘合成器 |
| PLL： | 是 |
| 主要目的： | PCI Express（PCIe） |
| 輸入： | 時(shí)鐘，晶體 |
| 輸出： | HCSL，LVDS |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:4 |
| 差分 - 輸入:輸出： | 無/是 |
| 頻率 - 最大： | 200MHz |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 20-TSSOP（0.173"，4.40mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 20-TSSOP |
| 包裝： | 管件 |
| 其它名稱： | 800-2584 |
IDT5V41066
4 OUTPUT PCIE GEN1/2 SYNTHESIZER
IDT 4 OUTPUT PCIE GEN1/2 SYNTHESIZER
5
IDT5V41066
REV D 112211
Output Structures
General PCB Layout Recommendations
For optimum device performance and lowest output phase
noise, the following guidelines should be observed.
1. Each 0.01F decoupling capacitor should be mounted on
the component side of the board as close to the VDD pin as
possible.
2. No vias should be used between decoupling capacitor
and VDD pin.
3. The PCB trace to VDD pin should be kept as short as
possible, as should the PCB trace to the ground via.
Distance of the ferrite bead and bulk decoupling from the
device is less critical.
4. An optimum layout is one with all components on the
same side of the board, minimizing vias through other signal
layers (any ferrite beads and bulk decoupling capacitors can
be mounted on the back). Other signal traces should be
routed away from the IDT5V41066.This includes signal
traces just underneath the device, or on layers adjacent to
the ground plane layer used by the device.
R
475
6*IREF
=2.3 mA
IREF
See Output Termination
Sections - Pages 3 ~ 5
Ω
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IDT5V41066PGGI8 | 制造商:Integrated Device Technology Inc 功能描述:IC CLK GEN SPRED SPECTRM 20TSSOP |
| IDT5V41067APGG | 功能描述:IC BUFFER MUX 2:4 20TSSOP RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 專用 系列:PCI Express® (PCIe) 標(biāo)準(zhǔn)包裝:1 系列:- 類型:時(shí)鐘/頻率發(fā)生器，多路復(fù)用器 PLL:是 主要目的:存儲(chǔ)器，RDRAM 輸入:晶體 輸出:LVCMOS 電路數(shù):1 比率 - 輸入:輸出:1:2 差分 - 輸入:輸出:無/是 頻率 - 最大:400MHz 電源電壓:3 V ~ 3.6 V 工作溫度:0°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:Digi-Reel® 其它名稱:296-6719-6 |
| IDT5V41067APGG8 | 制造商:Integrated Device Technology Inc 功能描述:IC CLK MUX PCIE 2 TO 4 20TSSOP |
| IDT5V41067APGGI | 制造商:Integrated Device Technology Inc 功能描述:IC CLK MUX PCIE 2 TO 4 20TSSOP |
| IDT5V41067APGGI8 | 制造商:Integrated Device Technology Inc 功能描述:IC CLK MUX PCIE 2 TO 4 20TSSOP |
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