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參數(shù)資料
| 型號(hào)： | IDT5V926PGGI |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時(shí)鐘產(chǎn)生/分配 |
| 英文描述： | 160 MHz, OTHER CLOCK GENERATOR, PDSO16 |
| 封裝： | GREEN, TSSOP-16 |
| 文件頁數(shù)： | 2/6頁 |
| 文件大?。?/td> | 54K |
| 代理商： | IDT5V926PGGI |
2
INDUSTRIALTEMPERATURERANGE
IDT5V926
SINGLEOUTPUTCLOCKGENERATOR
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
REFE
X1/REF
X2
VDD
VDDQ
QREF
VDDQ
S1
OE
GND
VDDQ
GND
QOUT
VDDQ
S0
GND
PIN CONFIGURATION
TSSOP
TOP VIEW
CRYSTAL SPECIFICATION
The crystal oscillators should be fundamental mode quartz crystals:
overtone crystals are not suitable. Crystal frequency should be specified
for parallel resonance with 50
Ω maximum equivalent series resonance.
Crystal tuning capacitors should be connected from X1/REF to GND and from
X2 to GND.
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
Description
Max.
Unit
VDD/VDDQ
Supply Voltage to Ground
– 0.5 to +4.6
V
VI
InputVoltage
– 0.5 to +4.6
V
IO
OutputCurrent
±50
mA
TSTG
StorageTemperature
– 65 to +150
° C
TJ
JunctionTemperature
150
° C
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
PIN DESCRIPTION
Pin Name Type
Description
S[1:0]
I
Three level divider/mode select pins. Float to MID.
OE
I
Output enable bar. Outputs QOUT and QREF are tristated when
HIGH. Set
OE LOW for normal operation (has internal pull-
down).
REFE
IQREF enable input. QREF stopped LOW when HIGH. When set
REFE LOW, the QREF is enabled (has internal pull-down).
X1/REF
I
Crystal oscillator input or clock input
X2
I
Crystal oscillator output. Leave unconnected for clock input.
QOUT
O
Output at N*REF frequency
QREF
O
Output at REF frequency
VDDQ
PWR
Power supply for the device outputs. Connect to VDD on PCB.
VDD
PWR
Power supply for the device core and inputs. Connect to VDD
on PCB.
GND
PWR
Ground supply
NOTES:
1.
H = HIGH
M = MEDIUM
L = LOW
2.
Test mode for low frequency testing. In this mode, REF clock bypasses the VCO (VCO powered down) and the crystal oscillator is powered down.
DIVIDE SELECTION TABLE(1)
S1
S0
Divide-by-N Value
Mode
L
2
PLL
L
M
3
PLL
L
H
4
PLL
M
L
4.25
PLL
M
5
PLL
M
H
6
PLL
H
L
6.25
PLL
H
M
8
PLL
H
TEST
TEST(2)
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