參數(shù)資料
型號： IDT5V9885TPFGI
廠商： IDT, Integrated Device Technology Inc
文件頁數(shù)： 5/39頁
文件大小： 0K
描述： IC CLOCK GEN PLL 500MHZ 32TQFP
標(biāo)準(zhǔn)包裝： 250
類型： *
PLL： 帶旁路
輸入： LVCMOS，LVTTL
輸出： LVCMOS，LVDS，LVPECL，LVTTL
電路數(shù)： 1
比率 - 輸入:輸出： 2:6
差分 - 輸入:輸出： 無/是
頻率 - 最大： 500MHz
除法器/乘法器： 是/無
電源電壓： 3 V ~ 3.6 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 32-LQFP
供應(yīng)商設(shè)備封裝： 32-TQFP（7x7）
包裝： 管件
其它名稱： 800-2579
13
INDUSTRIALTEMPERATURERANGE
IDT5V9885T
3.3V EEPROMPROGRAMMABLECLOCKGENERATOR
To determine if the loop is stable, the phase margin (ωm) would need to be calculated as follows.
Phase Margin:
ωz = 1 / (Rz * Cz)
(Eq. 23)
ωp =
Cz + Cp
(Eq. 24)
Rz * Cz * Cp
φm = (360 / 2π ) * [tan-1(ωc/ ωz) - tan-1(ωc/ ωp)]
(Eq. 25)
To ensure stability in the loop, the phase margin is recommended to be > 60° but too high will result in the lock time being excessively long. Certain loop filter
parameters would need to be compromised to not only meet a required loop bandwidth but to also maintain loop stability.
Example
Fc = 150KHz is the desired loop bandwidth. The total M value is 850. The ratio of ωp/ωc should be at least 4. A rule of thumb that will help to aid the way,
the ωp / ωc ratio should be at least 4. Given Fc and M, an optimal loop filter setting needs to be solved for that will meet both the PLL loop bandwidth and maintain
loopstability.
The charge pump gain should be relatively small as possible to achieve a low loop bandwidth.
Ip = 40uA .
Kφ * KVCO = 950MHz/V * 40uA = 38000A/Vs
Loop Bandwidths
ωc = 2π * Fc = 9.42x105 s-1
ωuz = ωp / ωc = 4
(Eq. 26)
ωc2 = ωp * ωz
(Eq. 27)
ωp =
Cz + Cp
= ωz (1 + Cz / Cp)
Rz * Cz * Cp
Solving for Cz, Cp, and Rz
Knowing ωc = Rz * Kφ* KVCO * Cz and substituting in the equations from above,
M * (Cz + Cp)
Cz >>> Cp, therefore, we can easily derive Cp to be
Cp = Kφ * KVCO
= 12.60pF
M * ωc2 * ωuz
Similarly for Cz and Rz
Cz =
Kφ * KVCO * (ωuz2 - 1) = Cp * (ωuz2 - 1) = 189pF
M * ωc2 * ωuz
Rz =
M * ωc * ωuz2
= 22.48K
Kφ * KVCO * (ωuz2 - 1)
Based on the loop filter parameter equations from above, since there are no possible values of 12.60pF for Cp, 189pF for Cz, and 22.48Kfor Rz, the next
possible values within the loop filter settings are 12.55pF (CP[3:0]=1111), 196.4pF (CZ[3:0]=0111), and 15.3K(RZ[3:0]=1111), respectively. This loop filter
setting will yield a loop bandwidth of about 102KHz. The phase margin must be checked for loop stability.
φm = (360 / 2π ) * [tan-1 (6.41x105 s-1 / 3.33x105 s-1) - tan-1 (6.41x105 s-1 / 5.54x106 s-1)] = 56°
Although slightly below 60°, the phase margin would be acceptable with a fairly stable loop.
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IDT5V9885TPFGI8 制造商:Integrated Device Technology Inc 功能描述:IC CLOCK GEN PLL 500MHZ 32TQFP
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IDT5V9888TNLGI8 制造商:Integrated Device Technology Inc 功能描述:IC CLOCK GEN PLL 500MHZ 28VFQFPN
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