參數(shù)資料
型號(hào): IDT5V991A-2JI
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: 時(shí)鐘及定時(shí)
英文描述: 3.3V PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK
中文描述: 5V SERIES, PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQCC32
封裝: PLASTIC, LCC-32
文件頁(yè)數(shù): 1/8頁(yè)
文件大小: 78K
代理商: IDT5V991A-2JI
1
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
IDT5V991A
3.3V PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK
S EPT EMBER 2001
2001 Integrated Device Technology, Inc.
DSC 5963/3
c
IDT5V991A
COMMERCIAL AND INDUS T RIAL T EMPERAT URE RANGES
3.3V PROGRAMMABLE
SKEW PLL CLOCK DRIVER
TURBOCLOCK
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
FEATURES:
REF is 5V tolerant
4 pairs of programmable skew outputs
Low skew: 200ps same pair, 250ps all outputs
Selectable positive or negative edge synchronization:
Excellent for DSP applications
Synchronous output enable
Output frequency: 3.75MHz to 85MHz
2x, 4x, 1/2, and 1/4 outputs
3 skew grades:
IDT5V991A-2: t
SKEW0
<250ps
IDT5V991A-5: t
SKEW0
<500ps
IDT5V991A-7: t
SKEW0
<750ps
3-level inputs for skew and PLL range control
PLL bypass for DC testing
External feedback, internal loop filter
12mA balanced drive outputs
Low Jitter: <200ps peak-to-peak
Available in 32-pin PLCC Package
DESCRIPTION:
The IDT5V991A is a high fanout 3.3V PLL based clock driver intended
for high performance computing and data-communications applications. A
key feature of the programmable skew is the ability of outputs to lead or lag
the REF input signal. The IDT5V991A has eight programmable skew
outputs in four banks of 2. Skew is controlled by 3-level input signals that
may be hard-wired to appropriate HIGH-MID-LOW levels.
When the GND/
sOE
pin is held low, all the outputs are synchronously
enabled. However, if GND/
sOE
is held high, all the outputs except 3Q0 and
3Q1 are synchronously disabled.
Furthermore, when the V
CCQ
/PE is held high, all the outputs are
synchronized with the positive edge of the REF clock input. When V
CCQ
/
PE is held low, all the outputs are synchronized with the negative edge of
REF. Both devices have LVTTL outputs with 12mA balanced drive outputs.
FUNCTIONAL BLOCK DIAGRAM
GND/sOE
1Q
0
Skew
Select
3
1Q
1
1F1:0
3
2Q
0
Skew
Select
3
2Q
1
2F1:0
FS
REF
PLL
FB
3
3Q
0
Skew
Select
3Q
1
3F1:0
3
3
4Q
0
4Q
1
Skew
Select
4F1:0
3
3
3
V
CCQ
/PE
相關(guān)PDF資料
PDF描述
IDT5V991A-5J Scan Test Devices With 20-Bit Universal Bus Transceivers 64-LQFP -40 to 85
IDT5V991A-5JG 3.3V PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK
IDT5V991A-5JI 3.3V PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK
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IDT5V991A-7JI 制造商:Integrated Device Technology Inc 功能描述:EIGHT DISTRIBUTED-OUTPUT CLOCK DRIVER, 32 Pin, Plastic, PLCC