參數(shù)資料
型號: IDT5V991A-7J
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: 時鐘及定時
英文描述: 3.3V PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK
中文描述: 5V SERIES, PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQCC32
封裝: PLASTIC, LCC-32
文件頁數(shù): 4/8頁
文件大?。?/td> 78K
代理商: IDT5V991A-7J
4
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
IDT5V991A
3.3V PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Symbol
V
IH
V
IL
V
IHH
V
IMM
V
ILL
I
IN
Parameter
Conditions
Min.
2
V
CC
0.6
V
CC
/2
0.3
Max.
0.8
Unit
V
V
V
V
V
μA
Input HIGH Voltage
Input LOW Voltage
Input HIGH Voltage
(1)
Input MID Voltage
(1)
Input LOW Voltage
(1)
Input Leakage Current
(REF, FB Inputs Only)
Guaranteed Logic HIGH (REF, FB Inputs Only)
Guaranteed Logic LOW (REF, FB Inputs Only)
3-Level Inputs Only
3-Level Inputs Only
3-Level Inputs Only
V
IN
= V
CC
or GND
V
CC
= Max.
V
IN
= V
CC
V
IN
= V
CC
/2
V
IN
= GND
V
CC
= Max., V
IN
= GND
V
CC
= Max., V
IN
= V
CC
V
CC
= Mn., I
OH
=
12mA
V
CC
= Mn., I
OL
= 12mA
V
CC
/2+0.3
0.6
±5
HIGH Level
MID Level
LOW Level
2.4
±200
±50
±200
±100
±100
0.55
I
3
3-Level Input DC Current (TEST, FS, nF
1:0
)
μA
I
PU
I
PD
V
OH
V
OL
Input Pull-Up Current (V
CCQ
/PE)
Input Pull-Down Current (GND/
sOE
)
Output HIGH Voltage
Output LOW Voltage
μA
μA
V
V
NOTE:
1.
These inputs are normally wired to V
CC
, GND, or unconnected. Internal termnation resistors bias unconnected inputs to V
CC
/2. If these inputs are switched, the function and
timng of the outputs may be glitched, and the PLL may require an additional t
LOCK
time before all datasheet limts are achieved.
RECOMMENDED OPERATING RANGE
IDT5V991A-2, -5, -7
(Industrial)
Min.
3
-40
IDT5V991A-2
(Commercial)
Min.
3
0
Symbol
Vcc
T
A
Description
Power Supply Voltage
Ambient Operating Temperature
Max.
3.6
+85
Max.
3.6
+70
Unit
V
°C
POWER SUPPLY CHARACTERISTICS
Symbol
Parameter
I
CCQ
Quiescent Power Supply Current
Test Conditions
(1)
Typ.
(2)
8
Max.
25
Unit
mA
V
CC
= Max., TEST = MID, REF = LOW,
V
CCQ
/PE = LOW, GND/
sOE
= LOW
All outputs unloaded
V
CC
= Max., V
IN
= 3V
V
CC
= Max., C
L
= 0pF
V
CC
= 3.3V, F
REF
= 20MHz, C
L
= 160pF
(1)
V
CC
= 3.3V, F
REF
= 33MHz, C
L
= 160pF
(1)
V
CC
= 3.3V, F
REF
= 66MHz, C
L
= 160pF
(1)
Δ
I
CC
I
CCD
I
TOT
Power Supply Current per Input HIGH
Dynamc Power Supply Current per Output
Total Power Supply Current
1
55
29
42
76
30
90
μ
A
μ
A/MHz
mA
NOTE:
1. For eight outputs, each loaded with 20pF.
INPUT TIMING REQUIREMENTS
Symbol
t
R
, t
F
Maximuminput rise and fall times, 0.8V to 2V
t
PWC
Input clock pulse, HIGH or LOW
D
H
Input duty cycle
R
EF
Reference Clock Input
Description
(1)
Min.
3
10
3.75
Max.
10
90
85
Unit
ns/V
ns
%
MHz
NOTE:
1. Where pulse width implied by D
H
is less than t
PWC
limt, t
PWC
limt applies.
相關PDF資料
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