- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄65576 > IDT5V994JGI (INTEGRATED DEVICE TECHNOLOGY INC) 5V SERIES, PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQCC32 PDF資料下載
參數(shù)資料
| 型號： | IDT5V994JGI |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時鐘及定時 |
| 英文描述： | 5V SERIES, PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQCC32 |
| 封裝： | GREEN, PLASTIC, LCC-32 |
| 文件頁數(shù)： | 8/9頁 |
| 文件大?。?/td> | 80K |
| 代理商： | IDT5V994JGI |
8
INDUSTRIALTEMPERATURERANGE
IDT5V994
3.3V PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK PLUS
RE F
FB
Q
OTHER Q
INV ER TE D Q
REF D IVIDE D B Y 2
REF D IVIDE D B Y 4
tREF
tSKEW2
tSKEW 3, 4
tSKEW1, 3, 4
tSKEW 2, 4
tSKEW 3, 4
tSKEW2
tSKEWPR
tSKEW 0, 1
tJR
tODCV
tRPWH
tRPW L
tSKEWPR
tSKEW 0, 1
t(φ)
AC TIMING DIAGRAM
NOTES:
PE:
The AC Timing Diagram applies to PE=VDD. For PE=GND, the negative edge of FB aligns with the negative edge of REF, divided outputs change on the negative edge
of REF, and the positive edges of the divide-by-2 and the divide-by-4 signals align.
Skew:
The time between the earliest and the latest output transition among all outputs for which the same tU delay has been selected when all are loaded with 20pF and terminated
with 75
Ω to VDDQ/2.
tSKEWPR:
The skew between a pair of outputs (xQ0 and xQ1) when all eight outputs are selected for 0tU.
tSKEW0:
The skew between outputs when they are selected for 0tU.
tDEV:
The output-to-output skew between any two devices operating under the same conditions (VDDQ, VDD, ambient temperature, air flow, etc.)
tODCV:
The deviation of the output from a 50% duty cycle. Output pulse width variations are included in tSKEW2 and tSKEW4 specifications.
tPWH is measured at 2V.
tPWL is measured at 0.8V.
tORISE and tOFALL are measured between 0.8V and 2V.
tLOCK:
The time that is required before synchronization is achieved. This specification is valid only after VDD/VDDQ is stable and within normal operating limits. This parameter
is measured from the application of a new signal or frequency at REF or FB until tPD is within specified limits.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| IDT5V994JI8 | 5V SERIES, PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQCC32 |
| IDT7217L16J8 | 16-BIT, DSP-MULTIPLIER, PQCC68 |
| IDT73201L20LB | 16-BIT, DSP-PIPELINE REGISTER, CQCC52 |
| IDT73201L15LB | 16-BIT, DSP-PIPELINE REGISTER, CQCC52 |
| IDT7321L20LB | 16-BIT, DSP-PIPELINE REGISTER, CQCC52 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IDT5V994JGI8 | 功能描述:IC CLK DVR PLL 3.3V PROGR 32PLCC RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:TurboClock™ Plus 標(biāo)準(zhǔn)包裝:1,000 系列:- 類型:時鐘/頻率合成器，扇出分配 PLL:- 輸入:- 輸出:- 電路數(shù):- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 除法器/乘法器:- 電源電壓:- 工作溫度:- 安裝類型:表面貼裝 封裝/外殼:56-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:56-VFQFP-EP（8x8） 包裝:帶卷 (TR) 其它名稱:844S012AKI-01LFT |
| IDT5V994JI | 制造商:Integrated Device Technology Inc 功能描述: |
| IDT5V994PFGI | 功能描述:IC CLK DVR PLL 3.3V PROGR 32TQFP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:TurboClock™ Plus 標(biāo)準(zhǔn)包裝:2,000 系列:- 類型:PLL 頻率合成器 PLL:是 輸入:晶體 輸出:時鐘 電路數(shù):1 比率 - 輸入:輸出:1:1 差分 - 輸入:輸出:無/無 頻率 - 最大:1GHz 除法器/乘法器:是/無 電源電壓:4.5 V ~ 5.5 V 工作溫度:-20°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-LSSOP（0.175"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-SSOP 包裝:帶卷 (TR) 其它名稱:NJW1504V-TE1-NDNJW1504V-TE1TR |
| IDT5V994PFGI8 | 功能描述:IC CLK DVR PLL 3.3V PROGR 32TQFP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:TurboClock™ Plus 標(biāo)準(zhǔn)包裝:1,000 系列:- 類型:時鐘/頻率合成器，扇出分配 PLL:- 輸入:- 輸出:- 電路數(shù):- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 除法器/乘法器:- 電源電壓:- 工作溫度:- 安裝類型:表面貼裝 封裝/外殼:56-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:56-VFQFP-EP（8x8） 包裝:帶卷 (TR) 其它名稱:844S012AKI-01LFT |
| IDT5V9950PFGI | 功能描述:IC CLK DVR PLL 1:8 200MHZ 32TQFP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:TurboClock™ II JR 標(biāo)準(zhǔn)包裝:1,000 系列:- 類型:時鐘/頻率合成器，扇出分配 PLL:- 輸入:- 輸出:- 電路數(shù):- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 除法器/乘法器:- 電源電壓:- 工作溫度:- 安裝類型:表面貼裝 封裝/外殼:56-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:56-VFQFP-EP（8x8） 包裝:帶卷 (TR) 其它名稱:844S012AKI-01LFT |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。