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參數(shù)資料
| 型號： | IDT5V9955BFGI |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時鐘及定時 |
| 英文描述： | 5V SERIES, PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PBGA96 |
| 封裝： | GREEN, FBGA-52 |
| 文件頁數(shù)： | 8/11頁 |
| 文件大?。?/td> | 127K |
| 代理商： | IDT5V9955BFGI |
6
INDUSTRIALTEMPERATURERANGE
IDT5V9955
3.3V PROGRAMMABLE SKEW DUAL PLL CLOCK DRIVER TURBOCLOCK W
POWER SUPPLY CHARACTERISTICS
Symbol
Parameter
Test Conditions(1)
Typ.(2)
Max.
Unit
IDDQ
Quiescent Power Supply Current
VDD = Max., TEST = MID, REF = LOW,
40
60
mA
xPE = LOW, x
sOE = LOW, xPD = HIGH
xFS = MID, All outputs unloaded
IDDPD
Power Down Current
VDD = Max.,
PD = LOW, xsOE = LOW
—
50
μA
xPE = HIGH, TEST = HIGH, xFS = HIGH
xnF[1:0] = HH, xDS[1:0] = HH
ΔIDD
Power Supply Current per Input HIGH
VIN = 3V, VDD = Max., x
PD = LOW, TEST = HIGH
1
60
μA
(REF and xFB inputs only)
xFS = L
190
290
IDDD
Dynamic Power Supply Current per Output
xFS = M
150
230
μA/MHz
xFS = H
130
200
xFS = L, FVCO = 50MHz, CL = 0pF
112
—
ITOT
Total Power Supply Current
xFS = M, FVCO = 100MHz, CL = 0pF
160
—
mA
xFS = H, FVCO = 200MHz, CL = 0pF
250
—
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Symbol
Parameter
Conditions(1)
Min.
Max.
Unit
VIH
Input HIGH Voltage
Guaranteed Logic HIGH (REF, xFB Inputs Only)
2
—
V
VIL
Input LOW Voltage
Guaranteed Logic LOW (REF, xFB Inputs Only)
—
0.8
V
VIHH
Input HIGH Voltage(2)
3-Level Inputs Only
VDD
0.6
—
V
VIMM
Input MID Voltage(2)
3-Level Inputs Only
VDD/2
0.3 VDD/2+0.3
V
VILL
Input LOW Voltage(2)
3-Level Inputs Only
—
0.6
V
IIN
InputLeakageCurrent
VIN = VDD or GND
5+5A
(REF, xFB Inputs Only)
VDD = Max.
VIN = VDD
HIGH Level
—
+400
I3
3-Level Input DC Current
VIN = VDD/2
MID Level
100
+100
A
(TEST, xFS, xnF[1:0], xDS[1:0])VIN = GND
LOW Level
400
—
IPU
Input Pull-Up Current (xPE, x
PD)VDD = Max., VIN = GND
25
—
A
IPD
Input Pull-Down Current (x
sOE)VDD = Max., VIN = VDD
—
+100
A
VOH
Output HIGH Voltage
VDD = Min., IOH =
2mA (xLOCK Output)
2.4
—
V
VDDQ = Min., IOH =
12mA (xnQ[1:0] Outputs)
2.4
—
VOL
Output LOW Voltage
VDD = Min., IOL = 2mA (xLOCK Output)
—
0.4
V
VDDQ = Min., IOL = 12mA (xnQ[1:0] Outputs)
—
0.4
NOTES:
1. All conditions apply to A and B banks.
2. These inputs are normally wired to VDD, GND, or unconnected. Internal termination resistors bias unconnected inputs to VDD/2. If these inputs are switched, the function and timing
of the outputs may be glitched, and the PLL may require an additional tLOCK time before all datasheet limits are achieved.
NOTES:
1. Measurements are for divide-by-1 outputs, xnF[1:0] = MM, and xDS[1:0] = MM. All conditions apply to A and B banks.
2. For nominal voltage and temperature.
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