參數(shù)資料
型號: IDT6167LA25DB
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: DRAM
英文描述: CMOS STATIC RAM 16K (16K x 1-BIT)
中文描述: 16K X 1 STANDARD SRAM, 25 ns, CDIP20
封裝: 0.300 INCH, CERDIP-20
文件頁數(shù): 4/8頁
文件大?。?/td> 63K
代理商: IDT6167LA25DB
5.2
4
IDT6167SA/LA
CMOS STATIC RAM 16K (16K x 1-BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS
V
CC
= 5.0V
±
10%
IDT6167SA
Min.
IDT6167LA
Min.
Symbol
Parameter
Test Condition
Max.
Max.
Unit
|I
LI
|
Input Leakage Current
V
CC
= Max.,
V
IN
= GND to V
CC
MIL
COM’L
10
5
5
2
μ
A
|I
LO
|
Output Leakage Current
V
CC
= Max.,
CS
= V
IH,
V
OUT
= GND to V
CC
MIL
COM’L
10
5
5
2
μ
A
V
OL
Output Low Voltage
I
OL
= 8mA, V
CC
= Min.
0.4
0.4
V
V
OH
Output High Voltage
I
OH
= –4mA, V
CC
= Min.
2.4
2.4
V
DATA RETENTION CHARACTERISTICS OVER ALL TEMPERATURE RANGES
(LA Version Only) V
LC
= 0.2V, V
HC
= V
CC
– 0.2V
Typ.
(1)
V
CC
@
Max.
V
CC
@
Symbol
V
DR
I
CCDR
Parameter
Test Condition
Min.
2.0
0
2.0v
0.5
0.5
3.0V
1.0
1.0
2.0V
200
20
3.0V
300
30
Unit
V
μ
A
V
CC
for Data Retention
Data Retention Current
MIL.
COM’L.
t
CDR
Chip Deselect to Data
Retention Time
Operation Recovery Time
CS
V
HC
VIN
V
HC
or
V
LC
ns
t
R(3)
|I
LI
|
(3)
t
RC(2)
ns
Input Leakage Current
2
2
μ
A
NOTES:
1. T
A
= +25
°
C.
2. t
RC
= Read Cycle Time.
3. This parameter is guaranteed by device characterization, but is not production tested.
2981 tbl 09
LOW V
CC
DATA RETENTION WAVEFORM
2981 tbl 08
2981 drw 03
DATA
RETENTION
MODE
4.5V
4.5V
V
DR
2V
V
IH
V
IH
t
R
t
CDR
V
CC
CS
V
DR
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
IDT6167LA25EB 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x1 SRAM
IDT6167LA25F 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x1 SRAM
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IDT6167LA25PDG 制造商:INTEGRATED DEVICE TECHNOLOGY 功能描述:IC SRAM 16K 6167 DIP20