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參數(shù)資料
| 型號(hào)： | IDT6168LA25D |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | DRAM |
| 英文描述： | CMOS STATIC RAM 16K (4K x 4-BIT) |
| 中文描述： | 4K X 4 STANDARD SRAM, 25 ns, CDIP20 |
| 封裝： | 0.300 INCH, CERDIP-20 |
| 文件頁(yè)數(shù)： | 4/9頁(yè) |
| 文件大小： | 91K |
| 代理商： | IDT6168LA25D |
4
IDT6168SA/LA
CMOS Static RAM 16K (4K x 4-Bit) Military, Industrial, and Commercial Temperature Ranges
Low V
CC
Data Retention Waveform
AC Test Conditions
Input Pulse Levels
Figure 1. AC Test Load
Figure 2. AC Test Load
(for t
CHZ
, t
CLZ
, t
WHZ
and t
OW
)
*Includes scope and jig capacitances
Data Retention Characteristics
(LA Version Only)
V
LC
= 0.2V, V
HC
= V
CC
0.2V
3090 drw 03
V
CC
CS
DATA
RETENTION
MODE
4.5V
4.5V
V
DR
≥
2V
V
IH
V
IH
t
R
t
CDR
V
DR
,
3090drw 04
480
30pF*
255
DATA
OUT
5V
3090 drw 05
480
5pF*
255
DATA
OUT
5V
Input Rise/Fall Times
Input Timng Reference Levels
Output Reference Levels
AC Test Load
GND to 3.0V
5ns
1.5V
1.5V
See Figures 1 and 2
3090 tbl 11
NOTES:
1. T
A
= +25°C.
2. at V
CC
= 2V
3. at V
CC
= 3V
4. t
RC
= Read Cycle Time.
5. This parameter is guaranteed by device characterization, but is not production tested.
IDT6168LA
Symbol
Parameter
Test Condition
Min.
Typ.
(1)
Max.
Unit
V
DR
V
CC
for Data Retention
2.0
____
____
V
I
CCDR
Data Retention Current
CS
> V
HC
V
IN
> V
HC
or < V
LC
MIL.
____
____
0.5
(2)
1.0
(3)
100
(2)
150
(3)
μ
A
COML.
____
____
0.5
(2)
1.0
(3)
20
(2)
30
(3)
μ
A
t
CDR
(5)
Chip Deselect to Data
Retention Time
0
____
____
ns
t
R
(5)
Operation Recovery Time
t
RC
(4)
____
____
ns
3090 tbl 10
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IDT6168LA25DB | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:CMOS STATIC RAM 16K (4K x 4-BIT) |
| IDT6168LA25EB | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x4 SRAM |
| IDT6168LA25F | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x4 SRAM |
| IDT6168LA25LB | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:CMOS STATIC RAM 16K (4K x 4-BIT) |
| IDT6168LA25P | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:CMOS STATIC RAM 16K (4K x 4-BIT) |
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