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參數(shù)資料
| 型號： | IDT6178S25Y |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | DRAM |
| 英文描述： | CMOS StaticRAM 16K (4K x 4-BIT) CACHE-TAG RAM |
| 中文描述： | 4K X 4 CACHE TAG SRAM, 25 ns, PDSO24 |
| 封裝： | 0.300 INCH, SOJ-24 |
| 文件頁數(shù)： | 1/7頁 |
| 文件大?。?/td> | 72K |
| 代理商： | IDT6178S25Y |
11.1
1
IDT6178S
CMOS StaticRAM 16K (4K x 4-BIT) CACHE-TAG RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGE
Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
MAY 1994
1994 Integrated Device Technology, Inc.
DSC-1059/2
1
CMOS StaticRAM
16K (4K x 4-BIT)
CACHE-TAG RAM
IDT6178S
FEATURES:
High-speed Address to MATCH Valid time
–
Military: 12/15/20/25ns
–
Commercial: 10/12/15/20/25ns (max.)
High-speed Address Access time
–
Military: 12/15/20/25ns
–
Commercial: 10/12/15/20/25ns (max.)
Low-power consumption
–
IDT6178S
Active: 300mW (typ.)
Produced with advanced CMOS high-performance
technology
Input and output TTL-compatible
Standard 22-pin Plastic or Ceramic DIP, 24-pin SOJ
Military product 100% compliant to MIL-STD-883,
Class B
DESCRIPTION:
The IDT6178 is a high-speed cache address comparator
sub-system consisting of a 16,384-bit StaticRAM organized
as 4K x 4. Cycle Time and Address to MATCH Valid are equal.
The IDT6178 features an onboard 4-bit comparator that
compares RAM contents and current input data. The result is
an active HIGH on the MATCH pin. The MATCH pins of
several IDT6178s can be handed together to provide enabling
or acknowledging signals to the data cache or processor.
The IDT6178 is fabricated using IDT’s high-performance,
high-reliability CMOS technology. Address to MATCH and
Data to MATCH times are as fast as 10ns.
All inputs and outputs of the IDT6178 are TTL-compatible
and the device operates from a single 5V supply.
The IDT6178 is packaged in either a 22-pin, 300-mil Plastic
or Ceramic DIP package or 24-pin SOJ. Military grade product
is manufactured in compliance with latest revision of MIL-
STD-883, Class B, making it ideally suited to military tempera-
ture applications demanding the highest level of performance
and reliability.
FUNCTIONAL BLOCK DIAGRAM
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
A
0
2953 drw 01
A
11
ADDRESS
DECODE
I/O
0
– I/O
3
WE
OE
CLR
CONTROL
16,384-BIT
MEMORY
ARRAY
CONTROL I/O
COMPARATOR
CLEAR
MEMORY
ARRAY
4
4
4
4
MATCH
V
CC
GND
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| IDT6178S | CMOS StaticRAM 16K (4K x 4-BIT) CACHE-TAG RAM |
| IDT6178S15D | Low-Power JFET-Input Operational Amplifier 8-PDIP 0 to 70 |
| IDT6178S15DB | Low-Power JFET-Input Operational Amplifier 8-PDIP 0 to 70 |
| IDT6178S15P | Dual Low-Power JFET-Input General-Purpose Operational Amplifier 8-SOIC 0 to 70 |
| IDT6178S15PB | Dual Low-Power JFET-Input General-Purpose Operational Amplifier 8-SOIC 0 to 70 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IDT6178S25YB | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:CMOS StaticRAM 16K (4K x 4-BIT) CACHE-TAG RAM |
| IDT61970L20D | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x4 SRAM |
| IDT61970L20DB | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x4 SRAM |
| IDT61970L20P | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x4 SRAM |
| IDT61970L20Y | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x4 SRAM |
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