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參數(shù)資料
| 型號(hào)： | IDT6198S25YB |
| 廠商： | Integrated Device Technology, Inc. |
| 英文描述： | CMOS STATIC RAM 64K (16K x 4-BIT) with Output Control |
| 中文描述： | 64K的的CMOS靜態(tài)RAM（16K的× 4位帶輸出）控制 |
| 文件頁(yè)數(shù)： | 4/8頁(yè) |
| 文件大?。?/td> | 79K |
| 代理商： | IDT6198S25YB |
6.3
4
IDT6198S/L
CMOS STATIC RAM 64K (16K x 4-BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DATA RETENTION CHARACTERISTICS OVER ALL TEMPERATURE RANGES
(L Version Only) V
LC
= 0.2V, V
HC
= V
CC
- 0.2V
Typ.
(1)
V
CC
@
Max.
V
CC
@
Symbol
V
DR
I
CCDR
Parameter
Test Condition
Min.
2.0
—
—
0
2.0v
—
10
10
—
3.0V
—
15
15
—
2.0V
—
600
150
—
3.0V
—
900
225
—
Unit
V
μ
A
V
CC
for Data Retention
Data Retention Current
—
MIL.
COM’L.
t
CDR(3)
Chip Deselect to Data
Retention Time
Operation Recovery Time
Input Leakage Current
CS
≥
V
HC
V
IN
≥
V
HC
or
≤
V
LC
ns
t
R(3)
|I
LI
|
(3)
t
RC(2)
—
—
—
—
—
—
2
—
2
ns
μ
A
NOTES:
1. T
A
= +25
°
C.
2. t
RC
= Read Cycle Time.
3. This parameter is guaranteed by device characterization but is not production tested.
2987 tbl 09
LOW V
CC
DATA RETENTION WAVEFORM
2987 drw 04
DATA
RETENTION
MODE
4.5V
4.5V
V
DR
≥
2V
V
IH
V
IH
t
R
t
CDR
V
CC
CS
V
DR
2987 drw 06
480
5pF*
255
DATA
OUT
5V
2987 drw 05
480
30pF*
255
DATA
OUT
5V
AC TEST CONDITIONS
Input Pulse Levels
GND to 3.0V
Input Rise/Fall Times
5ns
Input Timing Reference Levels
1.5V
Output Reference Levels
1.5V
AC Test Load
See Figures 1 and 2
2987 tbl 10
Figure 1. AC Test Load
Figure 2. AC Test Load
(for t
OLZ
, t
CLZ
, t
OHZ
, t
WHZ
, t
CHZ
and t
OW
)
*Includes scope and jig capacitances
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| IDT6198S30C | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x4 SRAM |
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