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參數(shù)資料
| 型號(hào)： | IDT7012S35L48B |
| 英文描述： | x9 Dual-Port SRAM |
| 中文描述： | X9熱賣雙端口SRAM |
| 文件頁(yè)數(shù)： | 15/15頁(yè) |
| 文件大?。?/td> | 190K |
| 代理商： | IDT7012S35L48B |
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6.42
IDT70V9379L
High-Speed 32K x 18 Dual-Port Synchronous Pipelined Static RAM
Industrial and Commercial Temperature Ranges
9
Timing Waveform with Port-to-Port Flow-Through Read(4,5,7)
Timing Waveform of a Bank Select Pipelined Read(1,2)
tSC
tHC
CE0(B1)
ADDRESS(B1)
A0
A1
A2
A3
A4
A5
tSA
tHA
CLK
4857 drw 08
Q0
Q1
Q3
DATAOUT(B1)
tCH2
tCL2
tCYC2
(3)
ADDRESS(B2)
A0
A1
A2
A3
A4
A5
tSA
tHA
CE0(B2)
DATAOUT(B2)
Q2
Q4
tCD2
tCKHZ
tCD2
tCKLZ
tDC
tCKHZ
tCD2
tCKLZ
(3)
tSC
tHC
(3)
tCKHZ
(3)
tCKLZ
(3)
tCD2
A6
tDC
tSC
tHC
tSC
tHC
DATAIN "A"
CLK "B"
R/
W "B"
ADDRESS "A"
R/
W "A"
CLK "A"
ADDRESS "B"
NO
MATCH
NO
MATCH
VALID
tCWDD
tCD1
tDC
DATAOUT "B"
4857 drw 09
VALID
tSW
tHW
tSA
tHA
tSD
tHD
tHW
tCD1
tCCS
tDC
tSA
tSW
tHA
(6)
NOTES:
1. B1 Represents Bank #1; B2 Represents Bank #2. Each Bank consists of one IDT70V9379 for this waveform, and are setup for depth expansion in this
example. ADDRESS(B1) = ADDRESS(B2) in this situation.
2.
UB, LB, OE, and ADS = VIL; CE1(B1), CE1(B2), R/W, CNTEN, and CNTRST = VIH.
3. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2).
4.
CE0, UB, LB, and ADS = VIL; CE1, CNTEN, and CNTRST = VIH.
5.
OE = VIL for the Right Port, which is being read from. OE = VIH for the Left Port, which is being written to.
6. If tCCS < maximum specified, then data from right port READ is not valid until the maximum specified for tCWDD.
If tCCS > maximum specified, then data from right port READ is not valid until tCCS + tCD1. tCWDD does not apply in this case.
7. All timing is the same for both Left and Right ports. Port "A" may be either Left or Right port. Port "B" is the opposite from Port "A".
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| IDT7012S45CB | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x9 Dual-Port SRAM |
| IDT7012S45F | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x9 Dual-Port SRAM |
| IDT7012S45FB | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x9 Dual-Port SRAM |
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