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參數(shù)資料
| 型號： | IDT7014S35J |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | DRAM |
| 英文描述： | Low-Power JFET-Input Operational Amplifier 8-SOIC 0 to 70 |
| 中文描述： | 4K X 9 DUAL-PORT SRAM, 35 ns, PQCC52 |
| 封裝： | PLASTIC, LCC-52 |
| 文件頁數(shù)： | 6/7頁 |
| 文件大?。?/td> | 72K |
| 代理商： | IDT7014S35J |
6.11
6
IDT7014S
HIGH-SPEED 4K x 9 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TABLE I – READ/WRITE CONTROL
Left or Right Port
(1)
OE
D
0-8
L
X
DATA
IN
H
L
DATA
OUT
X
H
Z
R/
W
Function
Data written into memory
Data in memory output on port
High-impedance outputs
NOTE:
1. A
OL
- A
11L
is not equal to A
OR
- A
11R.
'H' = HIGH,'L' = LOW, 'X' = Don’t Care, and 'Z' = High-impedance.
2528 tbl 10
TIMING WAVEFORM OF WRITE CYCLE
(1, 2, 3, 4, 5)
FUNCTIONAL DESCRIPTION
The IDT7014 provides two ports with separate control,
address, and I/O pins that permit independent access for
reads or writes to any location in memory. It lacks the chip
enable feature of most Dual-Ports, thus it operates in active
mode as soon as power is applied. Each port has its own
Output Enable control (
OE
). In the read mode, the port’s
OE
turns on the output drivers when set LOW. The user application
should avoid simultaneous write operations to the same
memory location. There is no on-chip arbitration circuitry to
resolve write priority and partial data from both ports may be
written. READ/WRITE conditions are illustrated in Table 1.
2528 drw 10
R/
W
t
WC
t
WP
t
DW
DATA
OUT
ADDRESS
DATA
IN
OE
t
AW
t
AS
(5)
t
WR
t
DH
t
OW
t
HZ(4)
(3)
(3)
t
WZ
(4)
NOTES:
1. R/
W
must be HIGH during all address transitions.
2. t
WR
is measured from R/
W
going HIGH to the end of write cycle.
3. During this period, the I/O pins are in the output state, and input signals must not be applied.
4. Transition is measured
±
200mV from the Low or High-impedance voltage with the Output Test Load (Figure 2).
5. If
OE
is LOW during a R/
W
controlled write cycle, the write pulse width must be the larger of t
WP
or (t
WZ
+ t
DW
) to allow the I/O drivers to turn off data to
be placed on the bus for the required t
DW
. If
OE
is HIGH during an R/
W
controlled write cycle, this requirement does not apply and the write pulse can
be as short as the specified t
WP
.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IDT7014S35PF | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:HIGH-SPEED 4K x 9 DUAL-PORT STATIC RAM |
| IDT7014S35XLB | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x9 Dual-Port SRAM |
| IDT7015 | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:HIGH-SPEED 8K x 9 DUAL-PORT STATIC RAM |
| IDT7015L | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:HIGH-SPEED 8K x 9 DUAL-PORT STATIC RAM |
| IDT7015L12G | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:HIGH-SPEED 8K x 9 DUAL-PORT STATIC RAM |
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