參數(shù)資料
型號: IDT7015L35GB
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: DRAM
英文描述: HIGH-SPEED 8K x 9 DUAL-PORT STATIC RAM
中文描述: 8K X 9 DUAL-PORT SRAM, 35 ns, CPGA68
封裝: CERAMIC, PGA-68
文件頁數(shù): 11/20頁
文件大小: 263K
代理商: IDT7015L35GB
IDT7015S/L
HIGH-SPEED 8K x 9 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
6.12
11
TIMING WAVEFORM OF SEMAPHORE READ AFTER WRITE TIMING, EITHER SIDE
(1)
NOTES:
1. D
OR
= D
OL
=V
IH
,
CE
R
=
CE
L
=V
IH
.
2. All timing is the same for left and right ports. Port “A” may be either left or right port. “B” is the opposite port from “A”.
3. This parameter is measured from R/
W
"A"
or
SEM
"A"
going high to R/
W
"B"
or
SEM
"B"
going High.
4. If t
SPS
is not satisfied, there is no guarantee which side will obtain the semaphore flag.
TIMING WAVEFORM OF SEMAPHORE WRITE CONTENTION
(1,3,4)
SEM
"A"
2954 drw 12
t
SPS
MATCH
R/
W
"A"
MATCH
A
0"A"
-A
2
"A"
SIDE
"A"
(2)
SEM
"B"
R/
W
"B"
SIDE
"B"
(2)
A
0"B"
-A
2
"B"
NOTES:
1.
CE
= V
IH
for the duration of the above timing (both write and read cycle).
2. "DATA
OUT
VALID" represents all I/O's (I/O
0
-I/O
8
) equal to the semaphore value.
SEM
2954 drw 11
t
AW
t
EW
t
SOP
I/O
VALID ADDRESS
t
SAA
R/
W
t
WR
t
OH
t
ACE
VALID ADDRESS
DATA
IN
VALID
DATA
OUT
VALID
(2)
t
DW
t
WP
t
DH
t
AS
t
SWRD
t
AOE
Read Cycle
Write Cycle
A
0
-A
2
OE
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