參數(shù)資料
型號: IDT7015L35J
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: DRAM
英文描述: HIGH-SPEED 8K x 9 DUAL-PORT STATIC RAM
中文描述: 8K X 9 DUAL-PORT SRAM, 35 ns, PQCC68
封裝: PLASTIC, LCC-68
文件頁數(shù): 14/20頁
文件大?。?/td> 263K
代理商: IDT7015L35J
6.12
14
IDT7015S/L
HIGH-SPEED 8K x 9 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE
(1)
IDT7015X12
Com'l. Only
Min.
IDT7015X15
Com'l. Only
Min.
IDT7015X17
Com'l. Only
Min
Symbol
INTERRUPT TIMING
t
AS
t
WR
t
INS
t
INR
Parameter
Max.
Max.
Max.
Unit
Address Set-up Time
Write Recovery Time
Interrupt Set Time
Interrupt Reset Time
0
0
12
12
0
0
15
15
0
0
17
17
ns
ns
ns
ns
WAVEFORM OF BUSY ARBITRATION CONTROLLED BY
CE
TIMING
(M/
S
= V
IH
)
(1)
WAVEFORM OF BUSY ARBITRATION CYCLE CONTROLLED BY ADDRESS MATCH TIMING
(M/
S
= V
IH
)
(1)
2954 drw 15
ADDR
"A"
and
"B"
ADDRESSES MATCH
CE
"A"
CE
"B"
BUSY
"B"
t
APS
t
BAC
t
BDC
(2)
2954 drw 16
ADDR
"A"
ADDRESS "N"
ADDR
"B"
BUSY
"B"
t
APS
t
BAA
t
BDA
(2)
MATCHING ADDRESS "N"
NOTES:
1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from “A”.
2. If t
APS
is not satisfied, the busy signal will be asserted on one side or another but there is no guarantee on which side busy will be asserted.
NOTE:
1. "X" in part numbers indicates power rating (S or L).
2739 tbl 14
IDT7015X20
IDT7015X25
IDT7015X35
Symbol
INTERRUPT TIMING
t
AS
t
WR
t
INS
t
INR
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Unit
Address Set-up Time
Write Recovery Time
Interrupt Set Time
Interrupt Reset Time
0
0
20
20
0
0
20
20
0
0
25
25
ns
ns
ns
ns
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IDT7015L35PF Low-Power JFET-Input Dual Operational Amplifier 20-LCCC -55 to 125
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