參數(shù)資料
型號: IDT7015S17PFB
廠商: Integrated Device Technology, Inc.
英文描述: HIGH-SPEED 8K x 9 DUAL-PORT STATIC RAM
中文描述: 高速8K的× 9雙端口靜態(tài)RAM
文件頁數(shù): 15/20頁
文件大小: 263K
代理商: IDT7015S17PFB
IDT7015S/L
HIGH-SPEED 8K x 9 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
6.12
15
TRUTH TABLE I — INTERRUPT FLAG
(1)
Left Port
R/
W
L
CE
L
OE
L
A
12L
-A
0L
L
L
X
X
X
X
X
X
X
X
L
L
Right Port
OE
R
INT
L
X
X
L
(3)
H
(2)
R/
W
R
X
X
L
X
CE
R
X
L
L
X
A
12R
-A
0R
INT
X
1FFF
1FFE
X
R
L
(2)
H
(3)
X
X
Function
1FFF
X
X
1FFE
X
L
X
X
Set Right
INT
R
Flag
Reset Right
INT
R
Flag
Set Left
INT
L
Flag
Reset Left
INT
L
Flag
NOTES:
1. Assumes
BUSY
L
=
BUSY
R
= V
IH
.
2. If
BUSY
L
= V
IL
, then no change.
3. If
BUSY
R
= V
IL
, then no change.
2954 tbl 15
WAVEFORM OF INTERRUPT TIMING
(1)
TRUTH TABLES
2954 drw 17
ADDR
"A"
INTERRUPT SET ADDRESS
CE
"A"
R/
W
"A"
t
AS
t
WC
t
WR
(3)
(4)
t
INS(3)
INT
"B"
(2)
2954 drw 18
ADDR
"B"
INTERRUPT CLEAR ADDRESS
CE
"B"
OE
"B"
t
AS
t
RC
(3)
t
INR
(3)
INT
"B"
(2)
NOTES:
1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from “A”.
2. See Interrupt truth table.
3. Timing depends on which enable signal (
CE
or R/
W
) is asserted last.
4. Timing depends on which enable signal (
CE
or R/
W
) is de-asserted first.
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