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參數(shù)資料
| 型號(hào)： | IDT7016L15PFB |
| 廠商： | Integrated Device Technology, Inc. |
| 英文描述： | Quad Low-Power JFET-Input General-Purpose Operational Amplifier 14-SO -40 to 85 |
| 中文描述： | 高速16K的× 9雙端口靜態(tài)RAM |
| 文件頁(yè)數(shù)： | 12/20頁(yè) |
| 文件大?。?/td> | 262K |
| 代理商： | IDT7016L15PFB |
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6.13
12
IDT7016S/L
HIGH-SPEED 16K x 9 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
BUSY TIMING (M/
S
= V
IL
)
BUSY
Input to Write
(4)
Write Hold After
BUSY
(5)
t
WB
0
—
0
—
0
—
ns
t
WH
15
—
17
—
25
—
ns
PORT-TO-PORT DELAY TIMING
Write Pulse to Data Delay
(1)
Write Data Valid to Read Data Delay
(1)
NOTES:
1. Port-to-port delay through RAM cells from writing port to reading port, refer to "Timing Waveformof Write with Port-to-Port Read and
BUSY
(M/
S
= V
IH
)".
2. To ensure that the earlier of the two ports wins.
3. t
BDD
is a calculated parameter and is the greater of 0, t
WDD
– t
WP
(actual), or t
DDD
– t
DW
(actual).
4. To ensure that the write cycle is inhibited on port "B" during contention on port "A".
5. To ensure that a write cycle is completed on port "B" after contention on port "A".
6. "X" in part numbers indicates power rating (S or L).
t
WDD
—
45
—
50
—
60
ns
t
DDD
—
30
—
30
—
35
ns
IDT7016X20
IDT7016X25
IDT7016X35
Symbol
BUSY TIMING (M/
S
= V
IH
)
t
BAA
BUSY
Access Time from Address Match
t
BDA
BUSY
Disable Time from Address Not Matched
t
BAC
BUSY
Access Time from Chip Enable Low
t
BDC
BUSY
Disable Time from Chip Enable High
Arbitration Priority Set-up Time
(2)
BUSY
Disable to Valid Data
(3)
Write Hold After
BUSY
(5)
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Unit
—
—
—
17
20
20
20
—
—
—
—
17
20
20
20
—
—
—
—
20
20
20
20
ns
ns
ns
ns
—
t
APS
5
—
5
—
5
—
ns
t
BDD
—
30
—
30
—
35
ns
t
WH
15
—
17
—
25
—
ns
AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE
(6)
IDT7016X12
Com'l. Only
Min.
IDT7016X15
Com'l. Only
Min.
Symbol
BUSY TIMING (M/
S
= V
IH
)
t
BAA
BUSY
Access Time from Address Match
t
BDA
BUSY
Disable Time from Address Not Matched
t
BAC
BUSY
Access Time from Chip Enable Low
t
BDC
BUSY
Disable Time from Chip Enable High
t
APS
Arbitration Priority Set-up Time
(2)
t
BDD
BUSY
Disable to Valid Data
(3)
t
WH
Write Hold After
BUSY
(5)
Parameter
Max.
Max.
Unit
—
—
—
—
5
—
11
12
12
12
12
—
15
—
—
—
—
—
5
—
13
15
15
15
15
—
18
—
ns
ns
ns
ns
ns
ns
ns
BUSY TIMING (M/
S
= V
IL
)
t
WB
BUSY
Input to Write
(4)
Write Hold After
BUSY
(5)
PORT-TO-PORT DELAY TIMING
Write Pulse to Data Delay
(1)
Write Data Valid to Read Data Delay
(1)
0
—
0
—
ns
t
WH
11
—
13
—
ns
t
WDD
—
25
—
30
ns
t
DDD
—
20
—
25
ns
2940 tbl 13
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| IDT7016L20G | Quad Low-Power JFET-Input General-Purpose Operational Amplifier 14-SO -40 to 85 |
| IDT7016L20GB | Quad Low-Power JFET-Input General-Purpose Operational Amplifier 14-SO -40 to 85 |
| IDT7016L20J | Quad Low-Power JFET-Input Operational Amplifier 14-SOIC 0 to 70 |
| IDT7016L20JB | Quad Low-Power JFET-Input Operational Amplifier 14-SOIC 0 to 70 |
| IDT7016L20PF | Quad Low-Power JFET-Input Operational Amplifier 14-SOIC 0 to 70 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IDT7016L15PFG | 制造商:IDT 制造商全稱(chēng):Integrated Device Technology 功能描述:HIGH-SPEED 16K X 9 DUAL-PORT STATIC RAM |
| IDT7016L15PFGB | 制造商:IDT 制造商全稱(chēng):Integrated Device Technology 功能描述:HIGH-SPEED 16K X 9 DUAL-PORT STATIC RAM |
| IDT7016L15PFGI | 制造商:IDT 制造商全稱(chēng):Integrated Device Technology 功能描述:HIGH-SPEED 16K X 9 DUAL-PORT STATIC RAM |
| IDT7016L17J | 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:x9 Dual-Port SRAM |
| IDT7016L17PF | 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:x9 Dual-Port SRAM |
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