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參數(shù)資料
| 型號： | IDT7016S25J |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | DRAM |
| 英文描述： | Low-Noise JFET-Input General-Purpose Operational Amplifier 8-PDIP 0 to 70 |
| 中文描述： | 16K X 9 DUAL-PORT SRAM, 25 ns, PQCC68 |
| 封裝： | PLASTIC, LCC-68 |
| 文件頁數(shù)： | 12/20頁 |
| 文件大?。?/td> | 262K |
| 代理商： | IDT7016S25J |
6.13
12
IDT7016S/L
HIGH-SPEED 16K x 9 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
BUSY TIMING (M/
S
= V
IL
)
BUSY
Input to Write
(4)
Write Hold After
BUSY
(5)
t
WB
0
—
0
—
0
—
ns
t
WH
15
—
17
—
25
—
ns
PORT-TO-PORT DELAY TIMING
Write Pulse to Data Delay
(1)
Write Data Valid to Read Data Delay
(1)
NOTES:
1. Port-to-port delay through RAM cells from writing port to reading port, refer to "Timing Waveformof Write with Port-to-Port Read and
BUSY
(M/
S
= V
IH
)".
2. To ensure that the earlier of the two ports wins.
3. t
BDD
is a calculated parameter and is the greater of 0, t
WDD
– t
WP
(actual), or t
DDD
– t
DW
(actual).
4. To ensure that the write cycle is inhibited on port "B" during contention on port "A".
5. To ensure that a write cycle is completed on port "B" after contention on port "A".
6. "X" in part numbers indicates power rating (S or L).
t
WDD
—
45
—
50
—
60
ns
t
DDD
—
30
—
30
—
35
ns
IDT7016X20
IDT7016X25
IDT7016X35
Symbol
BUSY TIMING (M/
S
= V
IH
)
t
BAA
BUSY
Access Time from Address Match
t
BDA
BUSY
Disable Time from Address Not Matched
t
BAC
BUSY
Access Time from Chip Enable Low
t
BDC
BUSY
Disable Time from Chip Enable High
Arbitration Priority Set-up Time
(2)
BUSY
Disable to Valid Data
(3)
Write Hold After
BUSY
(5)
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Unit
—
—
—
17
20
20
20
—
—
—
—
17
20
20
20
—
—
—
—
20
20
20
20
ns
ns
ns
ns
—
t
APS
5
—
5
—
5
—
ns
t
BDD
—
30
—
30
—
35
ns
t
WH
15
—
17
—
25
—
ns
AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE
(6)
IDT7016X12
Com'l. Only
Min.
IDT7016X15
Com'l. Only
Min.
Symbol
BUSY TIMING (M/
S
= V
IH
)
t
BAA
BUSY
Access Time from Address Match
t
BDA
BUSY
Disable Time from Address Not Matched
t
BAC
BUSY
Access Time from Chip Enable Low
t
BDC
BUSY
Disable Time from Chip Enable High
t
APS
Arbitration Priority Set-up Time
(2)
t
BDD
BUSY
Disable to Valid Data
(3)
t
WH
Write Hold After
BUSY
(5)
Parameter
Max.
Max.
Unit
—
—
—
—
5
—
11
12
12
12
12
—
15
—
—
—
—
—
5
—
13
15
15
15
15
—
18
—
ns
ns
ns
ns
ns
ns
ns
BUSY TIMING (M/
S
= V
IL
)
t
WB
BUSY
Input to Write
(4)
Write Hold After
BUSY
(5)
PORT-TO-PORT DELAY TIMING
Write Pulse to Data Delay
(1)
Write Data Valid to Read Data Delay
(1)
0
—
0
—
ns
t
WH
11
—
13
—
ns
t
WDD
—
25
—
30
ns
t
DDD
—
20
—
25
ns
2940 tbl 13
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| IDT7016S25JB | Low-Noise JFET-Input General-Purpose Operational Amplifier 8-PDIP 0 to 70 |
| IDT7016S25PF | Low-Noise JFET-Input General-Purpose Operational Amplifier 8-SO 0 to 70 |
| IDT7016S25PFB | Low-Noise JFET-Input General-Purpose Operational Amplifier 8-SO 0 to 70 |
| IDT7016S35G | Low-Noise JFET-Input General-Purpose Operational Amplifier 8-SO 0 to 70 |
| IDT7016S35GB | HIGH-SPEED 16K x 9 DUAL-PORT STATIC RAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IDT7016S25J8 | 功能描述:IC SRAM 144KBIT 25NS 68PLCC RoHS:否 類別:集成電路 (IC) >> 存儲器 系列:- 標準包裝:45 系列:- 格式 - 存儲器:RAM 存儲器類型:SRAM - 雙端口，異步 存儲容量:128K（8K x 16） 速度:15ns 接口:并聯(lián) 電源電壓:3 V ~ 3.6 V 工作溫度:0°C ~ 70°C 封裝/外殼:100-LQFP 供應商設(shè)備封裝:100-TQFP（14x14） 包裝:托盤 其它名稱:70V25S15PF |
| IDT7016S25JB | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:HIGH-SPEED 16K x 9 DUAL-PORT STATIC RAM |
| IDT7016S25JG | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:HIGH-SPEED 16K X 9 DUAL-PORT STATIC RAM |
| IDT7016S25JGB | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:HIGH-SPEED 16K X 9 DUAL-PORT STATIC RAM |
| IDT7016S25JGI | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:HIGH-SPEED 16K X 9 DUAL-PORT STATIC RAM |
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