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參數(shù)資料
| 型號： | IDT7016S35G |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | DRAM |
| 英文描述： | Low-Noise JFET-Input General-Purpose Operational Amplifier 8-SO 0 to 70 |
| 中文描述： | 16K X 9 DUAL-PORT SRAM, 35 ns, CPGA68 |
| 封裝： | CERAMIC, PGA-68 |
| 文件頁數(shù)： | 16/20頁 |
| 文件大?。?/td> | 262K |
| 代理商： | IDT7016S35G |
6.13
16
IDT7016S/L
HIGH-SPEED 16K x 9 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TRUTH TABLE II — ADDRESS BUSY
ARBITRATION
Inputs
A
0L
-A
13L
CE
L
CE
R
A
0R
-A
13R
X
X
NO MATCH
H
X
MATCH
X
H
MATCH
L
L
MATCH
Outputs
BUSY
L(1)
H
H
H
(2)
BUSY
R(1)
H
H
H
(2)
Function
Normal
Normal
Normal
Write Inhibit
(3)
NOTES:
1. Pins
BUSY
L
and
BUSY
R
are both outputs when the part is configured as a master. Both are inputs when configured as a slave.
BUSY
X
outputs on the
IDT7016 are push-pull, not open drain outputs. On slaves the
BUSY
X
input internally inhibits writes.
2. "L" if the inputs to the opposite port were stable prior to the address and enable inputs of this port. "H" if the inputs to the opposite port became stable
after the address and enable inputs of this port. If t
APS
is not met, either
BUSY
L
or
BUSY
R
= Low will result.
BUSY
L
and
BUSY
R
outputs can not be low
simultaneously.
3. Writes to the left port are internally ignored when
BUSY
L
outputs are driving low regardless of actual logic level on the pin. Writes to the right port are
internally ignored when
BUSY
R
outputs are driving low regardless of actual logic level on the pin.
3190 tbl 16
TRUTH TABLE III — EXAMPLE OF SEMAPHORE PROCUREMENT SEQUENCE
(1, 2)
Functions
D
0
- D
8
Left
No Action
1
Left Port Writes "0" to Semaphore
0
Right Port Writes "0" to Semaphore
0
Left Port Writes "1" to Semaphore
1
Left Port Writes "0" to Semaphore
1
Right Port Writes "1" to Semaphore
0
Left Port Writes "1" to Semaphore
1
Right Port Writes "0" to Semaphore
1
Right Port Writes "1" to Semaphore
1
Left Port Writes "0" to Semaphore
0
Left Port Writes "1" to Semaphore
1
D
0
- D
8
Right
Status
1
1
1
0
0
1
1
0
1
1
1
Semaphore free
Left port has semaphore token
No change. Right side has no write access to semaphore
Right port obtains semaphore token
No change. Left port has no write access to semaphore
Left port obtains semaphore token
Semaphore free
Right port has semaphore token
Semaphore free
Left port has semaphore token
Semaphore free
NOTES:
1. This table denotes a sequence of events for only one of the eight semaphores on the IDT7016.
2. There are eight semaphore flags written to via I/O
0
and read from all I/O's (I/O
0
-I/O
8
). These eight semaphores are addressed by A
0
- A
2
.
3190 tbl 17
memory location 3FFF and to clear the interrupt flag (
INT
R
),
the right port must access memory location 3FFF. The
message (9 bits) at 3FFE or 3FFF is user-defined since it is in
an addressable SRAM location. If the interrupt function is not
used, address locations 3FFE and 3FFF are not used as mail
boxes but are still part of the random access memory. Refer
to Truth Table for the interrupt operation.
BUSY LOGIC
Busy Logic provides a hardware indication that both ports
of the RAM have accessed the same location at the same
time. It also allows one of the two accesses to proceed and
signals the other side that the RAM is “Busy”. The busy pin can
then be used to stall the access until the operation on the other
side is completed. If a write operation has been attempted
from the side that receives a busy indication, the write signal
is gated internally to prevent the write from proceeding.
The use of busy logic is not required or desirable for all
FUNCTIONAL DESCRIPTION
The IDT7016 provides two ports with separate control,
address and I/O pins that permit independent access for reads
or writes to any location in memory. The IDT7016 has an
automatic power down feature controlled by
CE
. The
CE
controls on-chip power down circuitry that permits the respec-
tive port to go into a standby mode when not selected (
CE
High). When a port is enabled, access to the entire memory
array is permitted.
INTERRUPTS
If the user chooses to use the interrupt function, a memory
location (mail box or message center) is assigned to each port.
The left port interrupt flag (
INT
L
) is asserted when the right port
writes to memory location 3FFE where a write is defined as
the
CE
=
R/
W
=
V
IL
per the Truth Table. The left port clears
the interrupt by an address location 3FFE access when
CE
R
=
OE
R
=V
IL
, R/
W
is a "don't care". Likewise, the right port
interrupt flag (
INT
R
) is asserted when the left port writes to
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| IDT7016S35GB | HIGH-SPEED 16K x 9 DUAL-PORT STATIC RAM |
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相關(guān)代理商/技術(shù)參數(shù) |
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| IDT7016S35GB | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:HIGH-SPEED 16K x 9 DUAL-PORT STATIC RAM |
| IDT7016S35GG | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:HIGH-SPEED 16K X 9 DUAL-PORT STATIC RAM |
| IDT7016S35GGB | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:HIGH-SPEED 16K X 9 DUAL-PORT STATIC RAM |
| IDT7016S35GGI | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:HIGH-SPEED 16K X 9 DUAL-PORT STATIC RAM |
| IDT7016S35J | 功能描述:IC SRAM 144KBIT 35NS 68PLCC RoHS:否 類別:集成電路 (IC) >> 存儲(chǔ)器 系列:- 標(biāo)準(zhǔn)包裝:45 系列:- 格式 - 存儲(chǔ)器:RAM 存儲(chǔ)器類型:SRAM - 雙端口，異步 存儲(chǔ)容量:128K（8K x 16） 速度:15ns 接口:并聯(lián) 電源電壓:3 V ~ 3.6 V 工作溫度:0°C ~ 70°C 封裝/外殼:100-LQFP 供應(yīng)商設(shè)備封裝:100-TQFP（14x14） 包裝:托盤 其它名稱:70V25S15PF |
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