參數(shù)資料
型號(hào): IDT7016S
廠商: Integrated Device Technology, Inc.
英文描述: Low-Power JFET-Input Quad Operational Amplifier 20-LCCC -55 to 125
中文描述: 高速16K的× 9雙端口靜態(tài)RAM
文件頁數(shù): 15/20頁
文件大?。?/td> 262K
代理商: IDT7016S
IDT7016S/L
HIGH-SPEED 16K x 9 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
6.13
15
TRUTH TABLE I — INTERRUPT FLAG
(1)
Left Port
R/
W
L
CE
L
OE
L
A
13L
-A
0L
L
L
X
X
X
X
X
X
X
X
L
L
Right Port
OE
R
INT
L
X
X
L
(3)
H
(2)
R/
W
R
X
X
L
X
CE
R
X
L
L
X
A
13R
-A
0R
INT
X
3FFF
3FFE
X
R
L
(2)
H
(3)
X
X
Function
3FFF
X
X
3FFE
X
L
X
X
Set Right
INT
R
Flag
Reset Right
INT
R
Flag
Set Left
INT
L
Flag
Reset Left
INT
L
Flag
NOTES:
1. Assumes
BUSY
L
=
BUSY
R
= V
IH
.
2. If
BUSY
L
= V
IL
, then no change.
3. If
BUSY
R
= V
IL
, then no change.
3190 tbl 15
WAVEFORM OF INTERRUPT TIMING
(1)
TRUTH TABLES
3190 drw 17
ADDR
"A"
INTERRUPT SET ADDRESS
CE
"A"
R/
W
"A"
t
AS
t
WC
t
WR
(3)
(4)
t
INS(3)
INT
"B"
(2)
3190 drw 18
ADDR
"B"
INTERRUPT CLEAR ADDRESS
CE
"B"
OE
"B"
t
AS
t
RC
(3)
t
INR
(3)
INT
"B"
(2)
NOTES:
1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from “A”.
2. See Interrupt truth table.
3. Timing depends on which enable signal (
CE
or R/
W
) is asserted last.
4. Timing depends on which enable signal (
CE
or R/
W
) is de-asserted first.
相關(guān)PDF資料
PDF描述
IDT7016S12G Low-Power JFET-Input Quad Operational Amplifier 14-CDIP -55 to 125
IDT7016S12GB Low-Power JFET-Input Quad Operational Amplifier 14-CFP -55 to 125
IDT7016S12J Low-Power JFET-Input Quad Operational Amplifier 20-LCCC -55 to 125
IDT7016S12JB Low-Power JFET-Input Quad Operational Amplifier 20-LCCC -55 to 125
IDT7016S12PF Low-Power JFET-Input Quad Operational Amplifier 14-CDIP -55 to 125
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