參數資料
型號: IDT7024L70GB
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: DRAM
英文描述: HIGH-SPEED 4K x 16 DUAL-PORT STATIC RAM
中文描述: 4K X 16 DUAL-PORT SRAM, 70 ns, CPGA84
封裝: CERAMIC, PGA-84
文件頁數: 12/20頁
文件大?。?/td> 292K
代理商: IDT7024L70GB
6.15
12
IDT7024S/L
HIGH-SPEED 4K x 16 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT7024X15
Com'l Only
Min.
IDT7024X17 IDT7024X20
Com'l Only
Min.
Max.
IDT7024X25
Symbol
BUSY TIMING (M/
S
= V
IH
)
t
BAA
BUSY
Access Time from Address Match
t
BDA
BUSY
Disable Time from Address Not Matched
t
BAC
BUSY
Access Time from Chip Enable Low
t
BDC
BUSY
Disable Time from Chip Enable High
t
APS
Arbitration Priority Set-up Time
(2)
t
BDD
BUSY
Disable to Valid Data
(3)
t
WH
Write Hold After
BUSY
(5)
BUSY TIMING (M/
S
= V
IL
)
t
WB
BUSY
Input to Write
(4)
t
WH
Write Hold After
BUSY
(5)
Parameter
Max.
Min.
Max.
Min.
Max.
Unit
5
12
15
15
15
15
18
5
13
17
17
17
17
18
5
15
20
20
20
17
30
5
17
20
20
20
17
30
ns
ns
ns
ns
ns
ns
ns
0
12
0
13
0
15
0
17
ns
ns
PORT-TO-PORT DELAY TIMING
Write Pulse to Data Delay
(1)
t
DDD
Write Data Valid to Read Data Delay
(1)
t
WDD
30
25
30
25
45
35
50
35
ns
ns
BUSY TIMING (M/
S
= V
IL
)
t
WB
BUSY
Input to Write
(4)
t
WH
Write Hold After
BUSY
(5)
PORT-TO-PORT DELAY TIMING
t
WDD
Write Pulse to Data Delay
(1)
t
DDD
Write Data Valid to Read Data Delay
(1)
NOTES:
1. Port-to-port delay through RAM cells from writing port to reading port, refer to "Timing Waveform of Read With
BUSY
(M/
S
= V
IH
)" or "Timing Waveform
of Write With Port-To-Port Delay (M/
S
= V
IL
)".
2. To ensure that the earlier of the two ports wins.
3. tBDD is a calculated parameter and is the greater of 0ns, t
WDD
– t
WP
(actual), or t
DDD
– t
DW
(actual).
4. To ensure that the write cycle is inhibited on port "B" during contention with port "A".
5. To ensure that a write cycle is completed on port "B" after contention with port "A".
6. "X" in part numbers indicates power rating (S or L).
0
25
0
25
0
25
ns
ns
60
45
80
65
95
80
ns
ns
IDT7024X35
IDT7024X55
IDT7024X70
Mil. Only
Min.
Symbol
BUSY TIMING (M/
S
= V
IH
)
t
BAA
BUSY
Access Time from Address Match
t
BDA
BUSY
Disable Time from Address Not Matched
t
BAC
BUSY
Access Time from Chip Enable Low
t
BDC
BUSY
Disable Time from Chip Enable High
t
APS
Arbitration Priority Set-up Time
(2)
BUSY
Disable to Valid Data
(3)
Write Hold After
BUSY
(5)
Parameter
Min.
Max.
Min.
Max.
Max.
Unit
5
20
20
20
20
5
45
40
40
35
5
45
40
40
35
ns
ns
ns
ns
ns
t
BDD
35
40
45
ns
t
WH
25
25
25
ns
2740 tbl 15
AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE
(6)
相關PDF資料
PDF描述
IDT7024L70J HIGH-SPEED 4K x 16 DUAL-PORT STATIC RAM
IDT7024L70JB HIGH-SPEED 4K x 16 DUAL-PORT STATIC RAM
IDT7024L70PF HIGH-SPEED 4K x 16 DUAL-PORT STATIC RAM
IDT7024L70PFB HIGH-SPEED 4K x 16 DUAL-PORT STATIC RAM
IDT7024S70F HIGH-SPEED 4K x 16 DUAL-PORT STATIC RAM
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