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參數(shù)資料
| 型號(hào)： | IDT7024S17J |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | DRAM |
| 英文描述： | HIGH-SPEED 4K x 16 DUAL-PORT STATIC RAM |
| 中文描述： | 4K X 16 DUAL-PORT SRAM, 17 ns, PQCC84 |
| 封裝： | PLASTIC, LCC-84 |
| 文件頁數(shù)： | 16/20頁 |
| 文件大小： | 292K |
| 代理商： | IDT7024S17J |
6.15
16
IDT7024S/L
HIGH-SPEED 4K x 16 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TRUTH TABLE V — EXAMPLE OF SEMAPHORE PROCUREMENT SEQUENCE
(1,2)
Functions
D
0
- D
15
Left
No Action
1
Left Port Writes "0" to Semaphore
0
Right Port Writes "0" to Semaphore
0
Left Port Writes "1" to Semaphore
1
Left Port Writes "0" to Semaphore
1
Right Port Writes "1" to Semaphore
0
Left Port Writes "1" to Semaphore
1
Right Port Writes "0" to Semaphore
1
Right Port Writes "1" to Semaphore
1
Left Port Writes "0" to Semaphore
0
Left Port Writes "1" to Semaphore
1
NOTES:
1. This table denotes a sequence of events for only one of the eight semaphores on the IDT7024.
2. There are eight semaphore flags written to via I/O
0
and read from all the I/O's (I/O
0
-I/O
15
). These eight semaphores are addressed by A
0
- A
2
.
D
0
- D
15
Right
Status
1
1
1
0
0
1
1
0
1
1
1
Semaphore free
Left port has semaphore token
No change. Right side has no write access to semaphore
Right port obtains semaphore token
No change. Left port has no write access to semaphore
Left port obtains semaphore token
Semaphore free
Right port has semaphore token
Semaphore free
Left port has semaphore token
Semaphore free
TRUTH TABLE IV —
ADDRESS BUSY ARBITRATION
Inputs
A
0L
-A
11L
CE
L
CE
R
A
0R
-A
11R
X
X
NO MATCH
H
X
MATCH
X
H
MATCH
L
L
MATCH
Outputs
BUSY
L(1)
BUSY
R(1)
Function
Normal
Normal
Normal
Write Inhibit
(3)
H
H
H
(2)
H
H
H
(2)
NOTES:
1. Pins
BUSY
L
and
BUSY
R
are both outputs when the part is configured as a master. Both are inputs when configured as a slave.
BUSY
X
outputs on the
IDT7024 are push pull, not open drain outputs. On slaves, the
BUSY
asserted input internally inhibits write.
2. "L" if the inputs to the opposite port were stable prior to the address and enable inputs of this port. "H" if the inputs to the opposite port became stable
after the address and enable inputs of this port. If tAPS is not met, either
BUSY
L
or
BUSY
R
= Low will result.
BUSY
L
and
BUSY
R
outputs cannot be low
simultaneously.
3. Writes to the left port are internally ignored when
BUSY
L
outputs are driving low regardless of actual logic level on the pin. Writes to the right port are
internally ignored when
BUSY
R
outputs are driving low regardless of actual logic level on the pin.
2740 tbl 16
2740 tbl 19
FUNCTIONAL DESCRIPTION
The IDT7024 provides two ports with separate control,
address and I/O pins that permit independent access for reads
or writes to any location in memory. The IDT7024 has an
automatic power down feature controlled by
CE
. The
CE
controls on-chip power down circuitry that permits the
respective port to go into a standby mode when not selected
(
CE
High). When a port is enabled, access to the entire
memory array is permitted.
INTERRUPTS
If the user chooses to use the interrupt function, a memory
location (mail box or message center) is assigned to each port.
The left port interrupt flag (
INT
L
) is asserted when the right port
writes to memory location FFE (HEX), where a write is defined
as the
CE
= R/
W
= V
IL
per the Truth Table. The left port clears
the interrupt by access address location FFE access when
CE
R
=
OE
R =
V
IL,
R/
W
is a "don't care". Likewise, the right port
interrupt flag (
INT
R
) is asserted when the left port writes to
memory location FFF (HEX) and to clear the interrupt flag
(
INT
R
), the right port must access the memory location FFF.
The message (16 bits) at FFE or FFF is user-defined, since it
is an addressable SRAM location. If the interrupt function is
not used, address locations FFE and FFF are not used as mail
boxes, but as part of the random access memory. Refer to
Truth Table for the interrupt operation.
BUSY LOGIC
Busy Logic provides a hardware indication that both ports
of the RAM have accessed the same location at the same
time. It also allows one of the two accesses to proceed and
signals the other side that the RAM is “Busy”. The busy pin can
then be used to stall the access until the operation on the other
side is completed. If a write operation has been attempted
from the side that receives a busy indication, the write signal
is gated internally to prevent the write from proceeding.
The use of busy logic is not required or desirable for all
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