參數(shù)資料
型號(hào)： IDT7024S20PFB
廠商： INTEGRATED DEVICE TECHNOLOGY INC
元件分類： DRAM
英文描述： HIGH-SPEED 4K x 16 DUAL-PORT STATIC RAM
中文描述： 4K X 16 DUAL-PORT SRAM, 20 ns, PQFP100
封裝： TQFP-100
文件頁(yè)數(shù)： 10/20頁(yè)
文件大?。?/td> 292K
代理商： IDT7024S20PFB
6.15
10
IDT7024S/L
HIGH-SPEED 4K x 16 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF WRITE CYCLE NO. 1, R/
W
CONTROLLED TIMING
(1,5,8)
TIMING WAVEFORM OF WRITE CYCLE NO. 2,
CE
,
UB
,
LB
CONTROLLED TIMING
(1,5)
2740 drw 10
t
WC
t
AS
t
WR
t
DW
t
DH
ADDRESS
DATA
IN
R/
W
t
AW
t
EW
UB
or
LB
(3)
(2)
(6)
CE
or
SEM
(9)
(9)
R/
W
t
WC
t
HZ
t
AW
t
WR
t
AS
t
WP
DATA
OUT
(2)
t
WZ
t
DW
t
DH
t
OW
OE
ADDRESS
DATA
IN
(6)
(4)
(4)
(7)
UB
or
LB
2740 drw 09
(9)
CE
or
SEM
(9)
(7)
(3)
NOTES:
1. R/
W
or
CE
or
UB
&
LB
must be High during all address transitions.
2. A write occurs during the overlap (t
EW
or t
WP
) of a Low
UB
or
LB
and a Low
CE
and a Low R/
W
for memory array writing cycle.
3. t
WR
is measured from the earlier of
CE
or R/
W
(or
SEM
or R/
W
) going High to the end-of-write cycle.
4. During this period, the I/O pins are in the output state and input signals must not be applied.
5. If the
CE
or
SEM
Low transition occurs simultaneously with or after the R/
W
Low transition, the outputs remain in the High-impedance state.
6. Timing depends on which enable signal is asserted last,
CE
, R/
W
,
UB,
or
LB
.
7. This parameter is guaranted by device characterization, but is not production tested. Transition is measured +/- 500mV steady state with the Output Test
Load (Figure 2).
8. If
OE
is Low during R/
W
controlled write cycle, the write pulse width must be the larger of t
WP
for (t
WZ
+ t
DW
) to allow the I/O drivers to turn off and data
to be placed on the bus for the required t
DW
. If
OE
is High during an R/
W
controlled write cycle, this requirement does not apply and the write pulse
can be as short as the specified t
WP
.
9. To access RAM,
CE
= V
IL
,
UB
or
LB
= V
IL
, and
SEM
= V
IH
. To access Semaphore,
CE
= V
IH
or
UB
&
LB
= V
IH
, and
SEM
= V
IL
. t
EW
must be
met for either condition.
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