參數(shù)資料
型號: IDT7025L25PFB
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: DRAM
英文描述: 250V N-Channel MOSFET; ; No of Pins: 3; Container: Rail
中文描述: 8K X 16 DUAL-PORT SRAM, 25 ns, PQFP100
封裝: TQFP-100
文件頁數(shù): 7/20頁
文件大?。?/td> 294K
代理商: IDT7025L25PFB
IDT7025S/L
HIGH-SPEED 8K x 16 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
6.16
7
IDT7025X35
IDT7025X55
IDT7025X70
Mil. Only
Min.
Symbol
READ CYCLE
t
RC
t
AA
t
ACE
t
ABE
t
AOE
t
OH
t
LZ
t
HZ
t
PU
t
PD
t
SOP
t
SAA
Parameter
Min.
Max.
Min.
Max.
Max.
Unit
Read Cycle Time
Address Access Time
Chip Enable Access Time
(3)
Byte Enable Access Time
(3)
Output Enable Access Time
Output Hold from Address Change
Output Low-Z Time
(1, 2)
Output High-Z Time
(1, 2)
Chip Enable to Power Up Time
(1,2)
Chip Disable to Power Down Time
(1,2)
Semaphore Flag Update Pulse (
OE
or
SEM
)
Semaphore Address Access Time
(3)
35
3
3
0
15
35
35
35
20
15
35
35
55
3
3
0
15
55
55
55
30
25
50
55
70
3
3
0
15
70
70
70
35
30
50
70
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
NOTES:
1. Transition is measured
±
500mV from Low or High-impedance voltage with Output Test Load (Figure 2).
2. This parameter is guaranteed by device characterization, but is not production tested.
3. To access RAM,
CE
= V
IL,
UB
or
LB
= V
IL, and
SEM
= V
IH.
To access semephore,
CE
= V
IH or
UB
&
LB
= V
IH, and
SEM
= V
IL.
4. "X" in part numbers indicates power rating (S or L).
2683 tbl 13
AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE
(4)
IDT7025X15
Com'l. Only
Min. Max.
IDT7025X17
Com'l. Only
Min.
IDT7025X20
IDT7025X25
Symbol
READ CYCLE
t
RC
t
AA
t
ACE
t
ABE
t
AOE
t
OH
Parameter
Max.
Min.
Max.
Min.
Max.
Unit
Read Cycle Time
Address Access Time
Chip Enable Access Time
(3)
Byte Enable Access Time
(3)
Output Enable Access Time
Output Hold from Address Change
Output Low-Z Time
(1, 2)
Output High-Z Time
(1, 2)
Chip Enable to Power Up Time
(1,2)
Chip Disable to Power Down Time
(1,2)
15
3
15
15
15
10
17
3
17
17
17
10
20
3
20
20
20
12
25
3
25
25
25
13
ns
ns
ns
ns
ns
ns
t
LZ
3
3
3
3
ns
t
HZ
t
PU
0
10
0
10
0
12
0
15
ns
ns
t
PD
15
17
20
25
ns
t
SOP
t
SAA
Semaphore Flag Update Pulse (
OE
or
SEM
) 10
Semaphore Address Access
(3)
15
10
17
10
20
10
25
ns
ns
AC TEST CONDITIONS
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
GND to 3.0V
5ns Max.
1.5V
1.5V
Figures 1 and 2
2683 tbl 12
Figure 1. AC Output Test Load
Figure 2. Output Test Load
( for t
LZ
, t
HZ
, t
WZ
, t
OW
)
*
including scope and jig.
2683 drw 06
1250
30pF
775
5V
DATA
OUT
BUSY
INT
1250
5pF
775
5V
DATA
OUT
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