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參數(shù)資料
| 型號(hào)： | IDT70261L25PF |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | DRAM |
| 英文描述： | HIGH-SPEED 16K x 16 DUAL-PORT STATIC RAM WITH INTERRUPT |
| 中文描述： | 16K X 16 DUAL-PORT SRAM, 25 ns, PQFP100 |
| 封裝： | 14 X 14 MM, 1.40 MM HEIGHT, TQFP-100 |
| 文件頁數(shù)： | 11/19頁 |
| 文件大小： | 171K |
| 代理商： | IDT70261L25PF |
6.42
IDT70261S/L
High-Speed 16K x 16 Dual-Port Static RAM with Interrupt Industrial and Commercial Temperature Ranges
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NOTES:
1. Port-to-port delay through RAMcells fromwriting port to reading port, refer to "Timng Wave formof Write with Port-to-Port Read and
BUSY
(M/
S
= V
IH
)".
2. To ensure that the earlier of the two ports wins.
3. t
BDD
is a calculated parameter and is the greater of 0, t
WDD
–
t
WP
(actual), or t
DDD
–
t
DW
(actual).
4. To ensure that the write cycle is inhibited on port "B" during contention on port "A".
5. To ensure that a write cycle is completed on port "B" after contention on port "A".
6. 'X' in part numbers indicates power rating (S or L).
Symbol
Parameter
70261X15
Com'l Only
70261X20
Com'l & Ind
70261X25
Com'l & Ind
Unit
Min.
Max.
Min.
Max.
Min.
Max.
TIMING (M/ =V
IH
)
t
BAA
Access Time fromAddress Match
____
15
____
20
____
20
ns
t
BDA
Disable Time fromAddress Not Matched
____
15
____
20
____
20
ns
t
BAC
Access Time fromChip Enable Low
____
15
____
20
____
20
ns
t
BDC
Access Time fromChip Enable High
____
15
____
17
____
17
ns
t
APS
Arbitration Priority Set-up Time
(2)
5
____
5
____
5
____
ns
t
BDD
Disable to Valid Data
(3)
____
18
____
30
____
30
ns
t
WH
Write Hold After
(5)
12
____
15
____
17
____
ns
TIMING (M/ =V
IL
)
t
WB
Input to Write
(4)
0
____
0
____
0
____
ns
t
WH
Write Hold After
(5)
12
____
15
____
17
____
ns
PORT-TO-PORT DELAY TIMING
t
WDD
Write Pulse to Data Delay
(1)
____
30
____
45
____
50
ns
t
DDD
Write Data Valid to Read Data Delay
(1)
____
25
____
30
____
35
ns
3039 tbl 14a
Symbol
Parameter
70261X35
Com'l & Ind
70261X55
Com'l & Ind
Unit
Min.
Max.
Min.
Max.
TIMING (M/ =V
IH
)
t
BAA
Access Time fromAddress Match
____
20
____
45
ns
t
BDA
Disable Time fromAddress Not Matched
____
20
____
40
ns
t
BAC
Access Time fromChip Enable Low
____
20
____
40
ns
t
BDC
Access Time fromChip Enable High
____
20
____
35
ns
t
APS
Arbitration Priority Set-up Time
(2)
5
____
5
____
ns
t
BDD
Disable to Valid Data
(3)
____
35
____
40
ns
t
WH
Write Hold After
(5)
25
____
25
____
ns
TIMING (M/ =V
IL
)
t
WB
Input to Write
(4)
0
____
0
____
ns
t
WH
Write Hold After
(5)
25
____
25
____
ns
PORT-TO-PORT DELAY TIMING
t
WDD
Write Pulse to Data Delay
(1)
____
60
____
80
ns
t
DDD
Write Data Valid to Read Data Delay
(1)
____
45
____
65
ns
3039 tbl 14b
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