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參數(shù)資料
| 型號： | IDT7027L20G |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | DRAM |
| 英文描述： | HIGH-SPEED 32K x 16 DUAL-PORT STATIC RAM |
| 中文描述： | 32K X 16 DUAL-PORT SRAM, 20 ns, CPGA108 |
| 封裝： | CERAMIC, PGA-108 |
| 文件頁數(shù)： | 16/19頁 |
| 文件大?。?/td> | 160K |
| 代理商： | IDT7027L20G |
6.42
IDT7027S/L
High-Speed 32K x 16 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges
NOTES:
1. Pins
BUSY
L
and
BUSY
R
are both outputs when the part is configured as a master. Both are inputs when configured as a slave.
BUSY
outputs on the IDT7027 are
push-pull, not open drain outputs. On slaves the
BUSY
input internally inhibits writes.
2. "L" if the inputs to the opposite port were stable prior to the address and enable inputs of this port. "H" if the inputs to the opposite port became stable after the address
and enable inputs of this port. If t
APS
is not met, either
BUSY
L
or
BUSY
R
= LOW will result.
BUSY
L
and
BUSY
R
outputs can not be LOW simultaneously.
3. Writes to the left port are internally ignored when
BUSY
L
outputs are driving LOW regardless of the actual logic level on the pin. Writes to the right port are internally
ignored when
BUSY
R
outputs are driving LOW regardless of the actual logic level on the pin.
4. Refer to Chip Enable Truth Table.
NOTES:
1. This table denotes a sequence of events for only one of the eight semaphores on the IDT7027.
2. There are eight semaphore flags written to via I/O
0
and read fromall the I/O's (I/O
0
-I/O
15
). These eight semaphores are addressed by A
0
-A
2
.
3.
CE
= V
IH
,
SEM
= V
IL
, to access the semaphores. Refer to the Semaphore Read/Write Control Truth Table.
The IDT7027 provides two ports with separate control, address and
I/O pins that permt independent access for reads or writes to any location
in memory. The IDT7027 has an automatic power down feature controlled
by
CE
0
and CE
1
. The
CE
0
and
CE
1
control the on-chip power down
circuitry that permts the respective port to go into a standby mode when
not selected (
CE
= V
IH
). When a port is enabled, access to the entire
memory array is permtted.
'
If the user chooses the interrupt function, a memory location (mail box
or message center) is assigned to each port. The left port interrupt flag
(
INT
L
) is asserted when the right port writes to memory location 7FFE
(HEX), where a write is defined as
CE
R
= R/
W
R
= V
IL
per Truth Table
IV. The left port clears the interrupt through access of address location
7FFE when
CE
L
=
OE
L
= V
IL
, R/
W
is a "don't care". Likewise, the right port
interrupt flag (
INT
R
) is asserted when the left port writes to memory location
7FFF (HEX) and to clear the interrupt flag (
INT
R
), the right port must read
the memory location 7FFF. The message (16 bits) at 7FFE or 7FFF is
user-defined since it is an addressable SRAMlocation. If the interrupt
function is not used, address locations 7FFE and 7FFF are not used as
mail-boxes by ignoring the interrupt, but as part of the randomaccess
memory. Refer to Truth Table IV for the interrupt operation.
$%$&:'E)=/%/F
$%$&:E
,,&
@
Inputs
Outputs
Function
CE
L
CE
R
A
OL
-A
14L
A
OR
-A
14R
BUSY
L
(1)
BUSY
R
(1)
X
X
NO MATCH
H
H
Normal
H
X
MATCH
H
H
Normal
X
H
MATCH
H
H
Normal
L
L
MATCH
(2)
(2)
Write
Inhibit
(3)
3199 tbl 17
Functions
D
0
- D
15
Left
D
0
- D
15
Right
Status
No Action
1
1
Semaphore free
Left Port Writes "0" to Semaphore
0
1
Left port has semaphore token
Right Port Writes "0" to Semaphore
0
1
No change. Right side has no write access to semaphore
Left Port Writes "1" to Semaphore
1
0
Right port obtains semaphore token
Left Port Writes "0" to Semaphore
1
0
No change. Left port has no write access to semaphore
Right Port Writes "1" to Semaphore
0
1
Left port obtains semaphore token
Left Port Writes "1" to Semaphore
1
1
Semaphore free
Right Port Writes "0" to Semaphore
1
0
Right port has semaphore token
Right Port Writes "1" to Semaphore
1
1
Semaphore free
Left Port Writes "0" to Semaphore
0
1
Left port has semaphore token
Left Port Writes "1" to Semaphore
1
1
Semaphore free
3199 tbl 18
相關PDF資料 |
PDF描述 |
|---|---|
| IDT7027L20GB | HIGH-SPEED 32K x 16 DUAL-PORT STATIC RAM |
| IDT7027L20GI | HIGH-SPEED 32K x 16 DUAL-PORT STATIC RAM |
| IDT7027L20PF | HIGH-SPEED 32K x 16 DUAL-PORT STATIC RAM |
| IDT7027L20PFB | HIGH-SPEED 32K x 16 DUAL-PORT STATIC RAM |
| IDT7027L20PFI | HIGH-SPEED 32K x 16 DUAL-PORT STATIC RAM |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| IDT7027L20PF | 功能描述:IC SRAM 512KBIT 20NS 100TQFP RoHS:否 類別:集成電路 (IC) >> 存儲器 系列:- 標準包裝:1,000 系列:- 格式 - 存儲器:RAM 存儲器類型:SRAM - 雙端口，同步 存儲容量:1.125M（32K x 36） 速度:5ns 接口:并聯(lián) 電源電壓:3.15 V ~ 3.45 V 工作溫度:-40°C ~ 85°C 封裝/外殼:256-LBGA 供應商設備封裝:256-CABGA（17x17） 包裝:帶卷 (TR) 其它名稱:70V3579S5BCI8 |
| IDT7027L20PF8 | 功能描述:IC SRAM 512KBIT 20NS 100TQFP RoHS:否 類別:集成電路 (IC) >> 存儲器 系列:- 標準包裝:1,000 系列:- 格式 - 存儲器:RAM 存儲器類型:SRAM - 雙端口，同步 存儲容量:1.125M（32K x 36） 速度:5ns 接口:并聯(lián) 電源電壓:3.15 V ~ 3.45 V 工作溫度:-40°C ~ 85°C 封裝/外殼:256-LBGA 供應商設備封裝:256-CABGA（17x17） 包裝:帶卷 (TR) 其它名稱:70V3579S5BCI8 |
| IDT7027L20PFG | 制造商:Integrated Device Technology Inc 功能描述: |
| IDT7027L20PFGI | 功能描述:IC SRAM 512KBIT 20NS 100TQFP RoHS:是 類別:集成電路 (IC) >> 存儲器 系列:- 標準包裝:1,000 系列:- 格式 - 存儲器:RAM 存儲器類型:SRAM - 雙端口，同步 存儲容量:1.125M（32K x 36） 速度:5ns 接口:并聯(lián) 電源電壓:3.15 V ~ 3.45 V 工作溫度:-40°C ~ 85°C 封裝/外殼:256-LBGA 供應商設備封裝:256-CABGA（17x17） 包裝:帶卷 (TR) 其它名稱:70V3579S5BCI8 |
| IDT7027L20PFGI8 | 功能描述:IC SRAM 512KBIT 20NS 100TQFP RoHS:是 類別:集成電路 (IC) >> 存儲器 系列:- 標準包裝:1,000 系列:- 格式 - 存儲器:RAM 存儲器類型:SRAM - 雙端口，同步 存儲容量:1.125M（32K x 36） 速度:5ns 接口:并聯(lián) 電源電壓:3.15 V ~ 3.45 V 工作溫度:-40°C ~ 85°C 封裝/外殼:256-LBGA 供應商設備封裝:256-CABGA（17x17） 包裝:帶卷 (TR) 其它名稱:70V3579S5BCI8 |
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