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參數(shù)資料
| 型號(hào)： | IDT7028L15PF |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | DRAM |
| 英文描述： | HIGH-SPEED 64K x 16 DUAL-PORT STATIC RAM |
| 中文描述： | 64K X 16 DUAL-PORT SRAM, 15 ns, PQFP100 |
| 封裝： | 14 X 14 MM, 1.40 MM HEIGHT, TQFP-100 |
| 文件頁(yè)數(shù)： | 15/17頁(yè) |
| 文件大?。?/td> | 150K |
| 代理商： | IDT7028L15PF |
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6.42
IDT7028L
High-Speed 64K x 16 Dual-Port Static RAM Industrial and Commercial Temperature Ranges
2B
Busy Logic provides a hardware indication that both ports of the RAM
have accessed the same location at the same time. It also allows one of the
two accesses to proceed and signals the other side that the RAMis
“
busy
”
.
The
BUSY
pin can then be used to stall the access until the operation on
the other side is completed. If a write operation has been attempted from
the side that receives a
BUSY
indication, the write signal is gated internally
to prevent the write fromproceeding.
The use of
BUSY
logic is not required or desirable for all applications.
In some cases it may be useful to logically OR the
BUSY
outputs together
and use any
BUSY
indication as an interrupt source to flag the event of
an illegal or illogical operation. If the write inhibit function of
BUSY
logic is
not desirable, the
BUSY
logic can be disabled by placing the part in slave
mode with the M/
S
pin. Once in slave mode the
BUSY
pin operates solely
as a write inhibit input pin. Normal operation can be programmed by tying
the
BUSY
pins HIGH. If desired, unintended write operations can be
prevented to a port by tying the
BUSY
pin for that port LOW.
The
BUSY
outputs on the IDT7028 RAMin master mode, are push-
pull type outputs and do not require pull up resistors to operate. If these
RAMs are being expanded in depth, then the
BUSY
indication for the
resulting array requires the use of an external AND gate.
can result in a glitched internal write inhibit signal and corrupted data
in the slave.
14
The IDT7028 is an extremely fast Dual-Port 64K x16 CMOS Static
RAMwith an additional 8 address locations dedicated to binary semaphore
flags. These flags allow either processor on the left or right side of the Dual-
Port RAMto claima privilege over the other processor for functions defined
by the systemdesigner
’
s software. As an example, the semaphore can
be used by one processor to inhibit the other fromaccessing a portion of
the Dual-Port RAMor any other shared resource.
The Dual-Port RAMfeatures a fast access time, and both ports are
completely independent of each other. This means that the activity on the
left port in no way slows the access time of the right port. Both ports are
identical in function to standard CMOS Static RAMand can be read from
or written to, at the same time with the only possible conflict arising fromthe
simultaneous writing of, or a simultaneous READ/WRITE of, a non-
semaphore location. Semaphores are protected against such ambiguous
situations and may be used by the systemprogramto avoid any conflicts
in the non-semaphore portion of the Dual-Port RAM These devices have
an automatic power-down feature controlled by
CE
, the Dual-Port RAM
enable, and
SEM
, the semaphore enable. The
CE
and
SEM
pins control
on-chip power down circuitry that permts the respective port to go into
standby mode when not selected. This is the condition which is shown in
Truth Table II where
CE
and
SEM
are both HIGH.
Systems which can best use the IDT7028 contain multiple processors
or controllers and are typically very high-speed systems which are
software controlled or software intensive. These systems can benefit from
a performance increase offered by the IDT7028s hardware semaphores,
which provide a lockout mechanismwithout requiring complex program-
mng.
Software handshaking between processors offers the maximumin
systemflexibility by permtting shared resources to be allocated in varying
configurations. The IDT7028 does not use its semaphore flags to control
any resources through hardware, thus allowing the systemdesigner total
flexibility in systemarchitecture.
An advantage of using semaphores rather than the more common
methods of hardware arbitration is that wait states are never incurred in
either processor. This can prove to be a major advantage in very high-
speed systems.
+414:
The semaphore logic is a set of eight latches which are independent
of the Dual-Port RAM These latches can be used to pass a flag, or token,
fromone port to the other to indicate that a shared resource is in use. The
semaphores provide a hardware assist for a use assignment method
called
“
Token Passing Allocation.
”
In this method, the state of a semaphore
latch is used as a token indicating that shared resource is in use. If the left
processor wants to use this resource, it requests the token by setting the
latch. This processor then verifies its success in setting the latch by reading
it. If it was successful, it proceeds to assume control over the shared
resource. If it was not successful in setting the latch, it determnes that the
right side processor has set the latch first, has the token and is using the
shared resource. The left processor can then either repeatedly request
that semaphore
’
s status or remove its request for that semaphore to perform
:/47.2B
*91;2
When expanding an IDT7028 RAMarray in width while using
BUSY
logic, one master part is used to decide which side of the RAMs array will
receive a
BUSY
indication, and to output that indication. Any number of
slaves to be addressed in the same address range as the master, use
the
BUSY
signal as a write inhibit signal. Thus on the IDT7028 RAMthe
BUSY
pin is an output if the part is used as a master (M/
S
pin = V
IH
), and
the
BUSY
pin is an input if the part used as a slave (M/
S
pin = V
IL
) as shown
in Figure 3.
If two or more master parts were used when expanding in width, a split
decision could result with one master indicating
BUSY
on one side of the
array and another master indicating
BUSY
on one other side of the array.
This would inhibit the write operations fromone port for part of a word and
inhibit the write operations fromthe other port for the other part of the word.
The
BUSY
arbitration, on a master, is based on the chip enable and
address signals only. It ignores whether an access is a read or write. In
a master/slave array, both address and chip enable must be valid long
enough for a
BUSY
flag to be output fromthe master before the actual
write pulse can be initiated with the R/
W
signal. Failure to observe this timng
Figure 3. Busy and chip enable routing for both width and depth
expansion with IDT7028 RAMs.
4836drw 17
MASTER
Dual Port RAM
BUSY
R
CE
0
MASTER
Dual Port RAM
SLAVE
Dual Port RAM
SLAVE
Dual Port RAM
CE
1
CE
1
CE
0
A
16
BUSY
L
BUSY
R
BUSY
L
BUSY
R
BUSY
L
BUSY
R
BUSY
L
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