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參數(shù)資料
| 型號： | IDT707278S15PFI |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | DRAM |
| 英文描述： | Low-Noise JFET-Input Operational Amplifier 8-PDIP 0 to 70 |
| 中文描述： | 32K X 16 DUAL-PORT SRAM, 15 ns, PQFP100 |
| 封裝： | 14 X 14 MM, 1.40 MM HEIGHT, TQFP-100 |
| 文件頁數(shù)： | 8/16頁 |
| 文件大?。?/td> | 135K |
| 代理商： | IDT707278S15PFI |
6.42
IDT707278S/L
32K x 16 Bank-Switchable Dual-Ported SRAM with External Bank Selects Industrial and Commercial Temperature Ranges
8
NOTES:
1. Bank 0 refers to the first 8Kx16 memory spaces, Bank 1 to the second
8Kx16 memory spaces, Bank 2 to the third 8Kx16 memory spaces, and
Bank 3 to the fourth 8Kx16 memory spaces. 'LEFT' indicates the bank is
assigned to the left port; 'RIGHT' indicates the bank is assigned
right port. 0-4 banks may be assigned to either port.
2. The bank select pin inputs must be set at either V
IH
or V
IL
- these inputs are
not tri-statable. When changing the bank assignments, accesses of the
affected banks must be suspended. Accesses may continue uninterrupted
in banks that are not being reallocated.
3. 'H' = V
IH
, 'L' = V
IL
, 'X' = Don't Care.
to the
$1$
-(2
There are four bank select pins available on the IDT707278, and each
of these pins is associated with a specific bank within the memory array.
The pins are user-controlled inputs: access to a specific bank is assigned
to a particular port by setting the input to the appropriate level. The process
of assigning the banks is detailed in Truth Table IV. Once a bank is assigned
to a port, the owning port has full access to read and write within that bank.
The opposite port is unable to access that bank until the user reassigns the
port. Access by a port to a bank which it does not control will have no effect
#$#%&3'
CE
43
&;
"
!"
%(&*&
)
If the user chooses the mailbox interrupt function, four mailbox
locations are assigned to each port. These mail-box locations are external
to the memory array. The mailboxes are accessed bysetting
MBSEL
=
V
IL
while holding
CE
= V
IH
.
The mailboxes are 16 bits wide and controllable by byte: the message
is user-defined since these are addressable SRAMlocations. An interrupt
is generated to the opposite port upon writing to the upper byte of any
mailbox location. A port can read the message it has just written in order
to verify it: this read will not alter the status of the interrupt sent to the opposite
port. The interrupted port can clear the interrupt by reading the upper byte
of the applicable mailbox. This read will not alter the contents of the mailbox.
The use of mailboxes to generate interrupts to the opposite port and the
reading of mailboxes to clear interrupts is detailed in Truth Table V.
If desired, any of the mailbox interrupts can be independently masked
via software. Masking of the interrupt sources is done in the Mask Register.
The masks are individual and independent: a port can mask any
combination of interrupt sources with no effect on the other sources. Each
port can modify only its own Mask Register. The use of this register is
detailed in Truth Table V.
Two registers are provided to permt interpretation of interrupts: these
are the Interrupt Cause Register and the Interrupt Status Register. The
Interrupt Cause Register gives the user a snapshot of what has caused
the interrupt to be generated - the specific mailbox written to by the opposite
port. The information in this register provides post-mask signals: interrupt
sources that have been masked will not be updated. The Interrupt Status
Register gives the user the status of all bits that could potentially cause an
interrupt regardless of whether they have been masked. The use of the
Interrupt Cause Register and the Interrupt Status Register is detailed in
Truth Table V.
if written, and if read unknown values on D
0
-D
15
will be returned. Each
port can be assigned as many banks within the array as needed, up to
and including all four banks.
The bank select pin inputs must be set at either V
IH
or V
IL
- these inputs
are not tri-statable. When changing the bank assignments, accesses of the
affected banks must be suspended. Accesses may continue uninterrupted
in banks that are not being reallocated.
BKSEL0
BKSEL1
BKSEL2
BKSEL3
BANK AND
DIRECTION
(1)
H
X
X
X
BANK 0 LEFT
X
H
X
X
BANK 1 LEFT
X
X
H
X
BANK 2 LEFT
X
X
X
H
BANK 3 LEFT
L
X
X
X
BANK 0 RIGHT
X
L
X
X
BANK 1 RIGHT
X
X
L
X
BANK 2 RIGHT
X
X
X
L
BANK 3 RIGHT
3739 tbl 13
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