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參數(shù)資料
| 型號： | IDT707278S25PF |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | DRAM |
| 英文描述： | HIGH-SPEED 32K x 16 BANK-SWITCHABLE DUAL-PORTED SRAM WITH EXTERNAL BANK SELECTS |
| 中文描述： | 32K X 16 DUAL-PORT SRAM, 25 ns, PQFP100 |
| 封裝： | 14 X 14 MM, 1.40 MM HEIGHT, TQFP-100 |
| 文件頁數(shù)： | 4/16頁 |
| 文件大?。?/td> | 135K |
| 代理商： | IDT707278S25PF |
6.42
IDT707278S/L
32K x 16 Bank-Switchable Dual-Ported SRAM with External Bank Selects Industrial and Commercial Temperature Ranges
#$#%&'$-%
#$#%&&&'%()*+,
"
NOTES:
1. Chip Enable references are shown above with the actual
CE
0
and CE
1
levels,
CE
is a reference only.
2. Port "A" and "B" references are located where
CE
is used.
3. "H" = V
IH
and "L" = V
IL
.
4.
CE
and
MBSEL
cannot be active at the same time.
! ."
#$#%&&'/)*+,
NOTES:
1. BA
0L
- BA
1L
1 BA
0R
- BA
1R
: cannot access same bank simultaneously fromboth ports.
2. Refer to Truth Table I.
3.
CE
and
MBSEL
cannot both be active at the same time.
NOTES:
1. There are four mailbox locations per port written to and read fromall the I/O's (I/O
0
-I/O
15
). These four mailboxes are addressed by A
0
-A
5.
Refer
to Truth Table V.
2. Refer to Truth Table I.
3. Each mailbox location contains a 16-bit word, controllable in bytes by setting input levels to
UB
and
LB
appropriately.
CE
CE
0
CE
1
Mode
L
V
IL
V
IH
Port Selected (TTL Active)
< 0.2V
>V
CC
-0.2V
Port Selected (CMOS Active)
H
V
IH
X
Port Deselected (TTL Inactive)
X
V
IL
Port Deselected (TTL Inactive)
>V
CC
-0.2V
X
Port Deselected (CMOS Inactive)
X
<0.2V
Port Deselected (CMOS Inactive)
3739 tbl 02
Inputs
(1)
Outputs
Mode
CE
(2)
R/
W
OE
UB
LB
MBSEL
I/O
8-15
I/O
0-7
H
X
X
X
X
H
High-Z
High-Z
Deselcted: Power-Down
X
(3)
X
X
H
H
X
(3)
High-Z
High-Z
Both Bytes Deselected
L
L
X
L
H
H
DATA
IN
High-Z
Write to Upper Byte Only
L
L
X
H
L
H
High-Z
DATA
IN
Write to Lower Byte Only
L
L
X
L
L
H
DATA
IN
DATA
IN
Write to Both Bytes
L
H
L
L
H
H
DATA
OUT
High-Z
Read Upper Byte Only
L
H
L
H
L
H
High-Z
DATA
OUT
Read Lower Byte Only
L
H
L
L
L
H
DATA
OUT
DATA
OUT
Read Both Bytes
X
(3)
X
H
X
X
X
(3)
High-Z
High-Z
Outputs Disabled
3739 tbl 03
Inputs
Outputs
Mode
CE
(2)
R/
W
OE
UB
LB
MBSEL
I/O
8-15
I/O
0-7
H
H
L
X
(3)
X
(3)
L
DATA
OUT
DATA
OUT
Read Data fromMailbox,
↓
clears interrupt
H
H
L
L
L
L
DATA
OUT
DATA
OUT
Read Data fromMailbox,
↓
clears interrupt
H
L
X
L
(3)
L
(3)
L
DATA
IN
DATA
IN
Write Data into Mailbox
L
X
X
X
X
L
____
____
Not Allowed
3739 tbl 04
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| IDT707278S25PFI | HIGH-SPEED 32K x 16 BANK-SWITCHABLE DUAL-PORTED SRAM WITH EXTERNAL BANK SELECTS |
| IDT707278 | Dual Low-Noise JFET-Input General-Purpose Operational Amplifier 8-PDIP -40 to 85 |
| IDT707278L | Dual Low-Noise JFET-Input General-Purpose Operational Amplifier 8-PDIP -40 to 85 |
| IDT707278L15PF | Low-Noise JFET-Input Operational Amplifier 8-SOIC 0 to 70 |
| IDT707278L15PFI | Low-Noise JFET-Input Operational Amplifier 8-SOIC 0 to 70 |
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