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參數資料
| 型號： | IDT70824L20PF |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | DRAM |
| 英文描述： | HIGH-SPEED 4K X 16 SEQUENTIAL ACCESS RANDOM ACCESS MEMORY (SARAM⑩) |
| 中文描述： | 4K X 16 STANDARD SRAM, 20 ns, PQFP80 |
| 封裝： | TQFP-80 |
| 文件頁數： | 3/21頁 |
| 文件大?。?/td> | 205K |
| 代理商： | IDT70824L20PF |
6.42
IDT70824S/L
High-Speed 4K x 16 Sequential Access Random Access Memory Military and Commercial Temperature Ranges
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!
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!
NOTE
:
1. "I/O" is bidirectional Input and Output. "I" is Input and "O" is Output.
SYMBOL
NAME
I/O
DESCRIPTION
A
0
-A
11
Address Lines
I
Address inputs to access the 4096-word (16-Bit) memory array.
I/O
0
-I/O
15
Inputs/Outputs
I
Randomaccess data inputs/outputs for 16-Bit wde data.
CE
Chip Enable
I
When
CE
is LOW the randomaccess port is enabled. When
CE
is HIGH, the randomaccess port is disabled
into power-down mode and the I/O outputs are in the High-impedance state. All data is retained during
CE
=
V
IH
, unless it is altered by the sequential port
CE
and
CMD
may not be LOW at the same time.
CMD
Control Register Enable
I
When
CMD
is LOW address lines A
0
-A
2
, R/
W
, and inputs and outputs I/O
-I/O
12
, are used to access the
control register the flag register and the start and end of buffer registers.
CMD
and
CE
may not be LOW at the
same time.
R/
W
Read/Write Enable
I
If
CE
is LOW and
CMD
is HIGH, data is written into the array when R/
W
is LOW and read out of the array when
R/
W
is HIGH. If
CE
is HIGH and
CMD
is LOW R/
W
is used to access the buffer command registers.
CE
and
CMD
may not be LOW at the same time.
OE
Output Enable
I
When
OE
is LOW and R/
W
is HIGH, I/O
0
-I/O
15
outputs are enabled. When
OE
is HIGH, the I/O outputs are in
the High-impedance state.
LB
,
UB
Lower Byte, Upper Byte
Enables
I
When
LB
is LOW I/O
0
-I/O
7
are accessible for read and write operations. When
LB
is HIGH, I/O
0
-I/O
7
are tri-
stated and blocked during read and write operations.
UB
controls access for I/O
8
-I/O
15
in the same manner and
is asynchronous
from
LB
.
V
CC
Power Supply
I
Seven +5 power supply pins. All V
CC
pins must be connected to the same +5V V
CC
supply.
GND
Ground
I
Ten ground pins. All ground pins must be connected to the same ground supply.
3099 tbl 01
SYMBOL
NAME
I/O
DESCRIPTION
SI/O0-15
Inputs/Outputs
I/O
Sequential data inputs/outputs for 16-bit wde data.
SCLK
Clock
I
SI/O
0
-SI/O
15
,
SCE
, SR/
W
, and SLD are registered onthe LOW-to-HIGH transition of SCLK. Also, the sequential
access port address pointer increments by 1 on each LOW-TO-HIGH transition of SCLK when
CNTEN
is LOW
SCE
Chip Enable
I
When
SCE
is LOW the sequential access port is enabled on the LOW-to-HIGH transition of SCLK. When
SCE
is HIGH, the sequential access port is disabled into powered-down mode on the LOW-to-HIGH transition of
SCLK, and the SI/O outputs are in the High-impedance state. All data is retained, unless altered by the random
access port.
CNTEN
Counter Enable
I
When
CNTEN
is LOW the address pointer increments on the LOW-to-HIGH transition of SCLK. This function is
independent of
CE
.
SR/
W
Read/Write Enable
I
When SR/
W
and
SCE
are LOW a write cycle is initiated on the LOW-to-HIGH transitionof SCLK. When SR/
W
is
HIGH, and
SCE
and
SOE
are LOW a read cycle is initiated on the LOW-to-HIGH transition of SCLK. Termnation
of a write cycle is done on the LOW-to-HIGH transition of SCLK if SR/W or
SCE
is HIGH.
SLD
Address Pointer Load Control
I
When
SLD
is sampled LOW there is aninternal delay of one cycle before the address pointer changes. When
SLD
is LOW data on the inputs SI/O
0
-SI/O
11
is loaded into a data-in register on the LOW-to-HIGH transition of
SCLK. On the Cycle followng
SLD
, the address pointer charges to the address locationcontained in the data-
in register
SSTRT
1
and
SSTRT
2
may not be LOW while
SLD
is LOW or during the cycle followng
SLD
.
SSTRT
1
,
SSTRT
2
Load Start of Address
Register
I
When
SSTRT
1
or
SSTRT
2
is LOW the start of address register #1 or #2 is loaded into the address pointer on
the LOW-to-HIGH transition of SCLK. The start addresses are stored in internal registers.
SSTRT
1
and
SSTRT
2
may not be LOW while
SLD
is LOW or during the cycle followng
SLD
.
EOB
1
,
EOB
2
End of Buffer Flag
O
EOB
1
or
EOB
2
is output lowwhen the address pointer is incremented to matchthe address stored inthe end
of buffer registers. The flags can be cleared by either asserting
RST
LOW or by writing zero into Bit 0 and/or
Bit 1 of the control register at address 101.
EOB
1
and
EOB
2
are dependent onseparate internal registers, and
therefore separate match addresses.
SOE
Output Enable
I
SOE
controls the data outputs and is independent of SCLK. When
SOE
is LOW output buffers and the
sequentially addressed data is output. When
SOE
is HIGH, the SI/O output bus is in the High-impedance state.
SOE
is asynchronous to SCLK.
RST
Reset
I
When
RST
is LOW all internal registers are set to their default state, the address pointer is set to zero and the
EOB
1
and
EOB
2
flags are set HIGH.
RST
is asynchronous to SCLK.
3099 tbl 02
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