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參數(shù)資料
| 型號： | IDT70824L20PFB |
| 廠商： | Integrated Device Technology, Inc. |
| 英文描述： | HIGH-SPEED 4K X 16 SEQUENTIAL ACCESS RANDOM ACCESS MEMORY (SARAM⑩) |
| 中文描述： | 高速4K的× 16順序訪問隨機(jī)存取存儲器（單存取RAM⑩） |
| 文件頁數(shù)： | 9/21頁 |
| 文件大小： | 205K |
| 代理商： | IDT70824L20PFB |
6.42
IDT70824S/L
High-Speed 4K x 16 Sequential Access Random Access Memory Military and Commercial Temperature Ranges
RST
!
Setting
RST
LOW resets the control state of the SARAM
RST
functions
asynchronously of SCLK (i.e. not registered). The default states after a
reset operation are displayed in the adjacent chart.
,">'#
Within the SARAM the user can designate one of two buffer flow modes
for each buffer. Each buffer flow mode defines a unique set of actions for
the sequential port address pointer and
EOB
flags. In BUFFER CHAIN-
ING mode, after the address pointer reaches the end of the buffer, it sets
the corresponding
EOB
flag and continues fromthe start address of the
other buffer. In STOP mode, the address pointer stops incrementing after
it reaches the end of the buffer. There is no linear or mask mode available.
//C"$#5#
!
also allows reading and clearing the status of the
EOB
flags. Seven different
CMD
cases are available depending on the conditions of A
0
-A
2
and R/
W. Address bits A
3
-A
11
and data I/O bits I/O
12
-I/O
15
are not used during
this operation.
NOTE:
1. Start address and End of address for Buffer #2 and the Flow Control for
both Buffer #1 and #2, must be programmed as described in the "Buffer
Command Mode" section.
#'#
Buffer Command Mode (
CMD
) allows the randomaccess port to
control the state of the two buffers. Address pins A
0
-A
2
and I/O pins I/O
0
-
I/O
11
are used to access the start of buffer and the end of buffer addresses
and to set the flow control mode of each buffer. The Buffer Command Mode
CMD
!
#
CMD
'#
!
NOTES:
1. "H" = V
OH
for I/O in the output state and "Don't Cares" for I/O in the input state. "L" = V
IL
for I/O in the input state.
2. A write into the buffer occurs when R/
W
= V
IL
and a read when R/
W
= V
IH
.
EOB
1
/
SOB
1
and
EOB
2
/
SOB
2
are chosen through address A
0
-A
2
while
CMD
= V
IL
and
CE
= V
IH
.
NOTE:
1. R/
W
input "0(1)" indicates a write(0) or read(1) occurring with the same address input.
Register
Contents
Address
0
EOB
Flags
Cleared to HIGH state
Buffer FlowMode
BUFFER CHAINING
Start Address Buffer #1
0 (1)
End Address Buffer #1
4095 (4K)
Start Address Buffer #2
(1)
Cleared (set at invalid points)
End Address Buffer #2
(1)
Cleared (set at invalid points)
Registered State
SCE
= V
IH
, SR/
W
= V
IL
3099 tbl 15
Case #
A
2
-A
0
R/
W
DESCRIPTIONS
1
000
0 (1)
Write (read) the start address of Buffer #1 through I/O
0
-I/O
11
.
2
001
0 (1)
Write (read) the end address of Buffer #1 through I/O
0
-I/O
11
.
3
010
0 (1)
Write (read) the start address of Buffer #2 through I/O
0
-I/O
11
.
4
011
0 (1)
Write (read) the end address of Buffer #2 through I/O
0
-I/O
11
.
5
100
0 (1)
Write (read) flowcontrol register
6
101
0
Write only - clear
EOB
1
and/or
EOB
2
flag.
7
101
1
Read only - flag status register
8
110/111
(X)
(Reserved)
3099 tbl 16
15
MSB
LSB I/O BITS
3099 drw 10
H
H
11 --------------------------------------------------------------------------------------------------
Address Loaded into Buffer
0
14
13
H
L
12
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