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參數(shù)資料
| 型號(hào)： | IDT70825S35PFB |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | DRAM |
| 英文描述： | Quad Low-Noise JFET-Input General-Purpose Operational Amplifier 14-SO 0 to 70 |
| 中文描述： | 8K X 16 STANDARD SRAM, 35 ns, PQFP80 |
| 封裝： | TQFP-80 |
| 文件頁數(shù)： | 9/21頁 |
| 文件大?。?/td> | 319K |
| 代理商： | IDT70825S35PFB |
IDT70825S/L
HIGH-SPEED 8K x 16 SEQUENTIAL ACCESS RANDOM ACCESS MEMORY
MILITARY AND COMMERCIAL TEMPERATURE RANGES
6.31
9
CASE 5: BUFFER FLOW MODES
Within the SARAM, the user can designate one of four
buffer flow modes for each buffer. Each buffer flow mode
defines a unique set of actions for the sequential port address
pointer and EOB flags. In BUFFER CHAINING mode, after the
address pointer reaches the end of the buffer, it sets the
corresponding EOB flag and continues from the start address
of the other buffer. In STOP mode, the address pointer stops
incrementing after it reaches the end of the buffer. In LINEAR
mode, the address pointer ignores the end of buffer address
and increments past it, but sets the EOB flag. MASK mode is
the same as LINEAR mode except EOB flags are not set.
CASES 1 THROUGH 4: START AND END OF BUFFER REGISTER DESCRIPTION
(1,2)
15
MSB
LSB I/O BITS
3016 drw 10
H
H
12 ------------------------------------------------------------------------------------------------------------
Address Loaded into Buffer
0
14
13
H
reading and clearing the status of the EOB flags. Seven
different CMD cases are available depending on the condi-
tions of A
0
-A
2
and R/W. Address bits A
3
-A
12
and data I/O bits
I/O
13
-I/O
15
are not used during this operation.
RANDOM ACCESS PORT
CMD
MODE
(1)
Case #
1
2
3
4
5
6
7
8
A2-A0
000
001
010
011
100
101
101
110/111
R/
W
0 (1)
0 (1)
0 (1)
0 (1)
0 (1)
0
1
(X)
DESCRIPTIONS
Write (read) the start address of Buffer #1 through I/O
0
-I/O
12
.
Write (read) the end address of Buffer #1 through I/O
0
-I/O
12
.
Write (read) the start address of Buffer #2 through I/O
0
-I/O
12
.
Write (read) the end address of Buffer #2 through I/O
0
-I/O
12
.
Write (read) flow control register
Write only – clear EOB
1
and/or EOB
2
flag
Read only – flag status register
(Reserved)
NOTE:
1. R/
W
input "0(1)" indicates a write(0) or read(1) occurring with the same address input.
3016 tbl 16
Register
Contents
0
Address Pointer
EOB Flags
Buffer Flow Mode
Start Address Buffer #1
End Address Buffer #1
Start Address Buffer #2
End Address Buffer #2
Registered State
Cleared to High state
BUFFER CHAINING
0
4095
4096
8191
SCE
= V
IH
, SR/
W
= V
IL
(1)
(4K)
(4K+1)
(8K)
3016 tbl 15
Reset (
Setting
RST
LOW resets the control state of the SARAM.
RST
functions asynchronously of SCLK, (i.e. not registered).
The default states after a reset operation are as follows:
RST
)
BUFFER COMMAND MODE (
Buffer Command Mode (
CMD
) allows the random access
port to control the state of the two buffers. Address pins A
0
-A
2
and I/O pins I/O
0
-I/O
12
are used to access the start of buffer
and the end of buffer addresses and to set the flow control
mode of each buffer. The Buffer Command Mode also allows
CMD
)
NOTES:
1. "H" = V
OH
for I/O in the output state and "Don't Cares" for I/O in the input state.
2. A write into the buffer occurs when R/
W
= V
IL
and a read when R/
W
= V
IH
.
EOB
1/
SOB
1 and
EOB
2/
SOB
2 are chosen through address A0-A2 while
CMD
= V
IL
and
CE
= V
IH
.
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