參數(shù)資料
型號: IDT70P248L55BYI
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: DRAM
英文描述: VERY LOW POWER 1.8V 8K/4K x 16 DUAL-PORT STATIC RAM
中文描述: 4K X 16 DUAL-PORT SRAM, 55 ns, PBGA100
封裝: 6 X 6 MM, 1 MM HEIGHT, 0.50 MM PITCH, BGA-100
文件頁數(shù): 4/15頁
文件大?。?/td> 190K
代理商: IDT70P248L55BYI
6.42
IDT70V9379L
High-Speed 32K x 18 Dual-Port Synchronous Pipelined Static RAM
Industrial and Commercial Temperature Ranges
12
Timing Waveform of Pipelined Read with Address Counter Advance(1)
Timing Waveform of Flow-Through Read with Address Counter Advance(1)
NOTES:
1.
CE0, OE, UB, and LB = VIL; CE1, R/W, and CNTRST = VIH.
2. If there is no address change via
ADS = VIL (loading a new address) or CNTEN = VIL (advancing the address), i.e. ADS = VIH and CNTEN = VIH, then the data
output remains constant for subsequent clocks.
ADDRESS
An
CLK
DATAOUT
Qx - 1
(2)
Qx
Qn
Qn + 2
(2)
Qn + 3
ADS
CNTEN
tCYC2
tCH2
tCL2
4857 drw 14
tSA
tHA
tSAD tHAD
tCD2
tDC
READ
EXTERNAL
ADDRESS
READ WITH COUNTER
COUNTER
HOLD
tSAD tHAD
tSCN tHCN
READ
WITH
COUNTER
Qn + 1
ADDRESS
An
CLK
DATAOUT
Qx
(2)
Qn
Qn + 1
Qn + 2
Qn + 3
(2)
Qn + 4
ADS
CNTEN
tCYC1
tCH1
tCL1
4857 drw 15
tSA
tHA
tSAD tHAD
READ
EXTERNAL
ADDRESS
READ WITH COUNTER
COUNTER
HOLD
tCD1
tDC
tSAD tHAD
tSCN tHCN
READ
WITH
COUNTER
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