參數(shù)資料
型號(hào): IDT70V24L55G
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: DRAM
英文描述: HIGH-SPEED 3.3V 4K x 16 DUAL-PORT STATIC RAM
中文描述: 4K X 16 DUAL-PORT SRAM, 55 ns, CPGA84
封裝: 1.120 X 1.120 INCH, 0.160 INCH HEIGHT, CERAMIC, PGA-84
文件頁數(shù): 11/17頁
文件大?。?/td> 281K
代理商: IDT70V24L55G
6.38
11
IDT70V24S/L
HIGH-SPEED 3.3V 4K x 16 DUAL-PORT STATIC RAM
COMMERCIAL TEMPERATURE RANGE
TIMING WAVEFORM OF SLAVE WRITE (M/
S
= V
IH
)
2911 drw 13
R/
W
"A"
BUSY
"B"
t
WP
t
WB
R/
W
"B"
t
WH
(2)
(3)
(1)
NOTES:
1. t
WH
must be met for both
BUSY
input (slave) and output (master).
2. Busy is asserted on port "B" Blocking R/
W
"B", until
BUSY
"B" goes High.
3. t
WB
is only for the "slave" version.
2911 drw 14
ADDR
"A"
and
"B"
ADDRESSES MATCH
CE
"A"
CE
"B"
BUSY
"B"
t
APS
t
BAC
t
BDC
(2)
WAVEFORM OF BUSY ARBITRATION CONTROLLED BY
CE
TIMING(M/
S
= V
IH
)
(1)
2911 drw 15
ADDR
"A"
ADDRESS "N"
ADDR
"B"
BUSY
"B"
t
APS
t
BAA
t
BDA
(2)
MATCHING ADDRESS "N"
WAVEFORM OF BUSY ARBITRATION CYCLE CONTROLLED BY ADDRESS MATCH TIMING
(M/
S
= V
IH
)
(1)
NOTES:
1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from “A”.
2. If t
APS
is not satisfied, the busy signal will be asserted on one side or another but there is no guarantee on which side busy will be asserted.
相關(guān)PDF資料
PDF描述
IDT70V24L55J HIGH-SPEED 3.3V 4K x 16 DUAL-PORT STATIC RAM
IDT70V24L55PF HIGH-SPEED 3.3V 4K x 16 DUAL-PORT STATIC RAM
IDT70V24S25G HIGH-SPEED 3.3V 4K x 16 DUAL-PORT STATIC RAM
IDT70V24S25J HIGH-SPEED 3.3V 4K x 16 DUAL-PORT STATIC RAM
IDT70V24S25PF HIGH-SPEED 3.3V 4K x 16 DUAL-PORT STATIC RAM
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