- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄377282 > IDT70V24S35G (INTEGRATED DEVICE TECHNOLOGY INC) HIGH-SPEED 3.3V 4K x 16 DUAL-PORT STATIC RAM PDF資料下載
參數(shù)資料
| 型號(hào)： | IDT70V24S35G |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | DRAM |
| 英文描述： | HIGH-SPEED 3.3V 4K x 16 DUAL-PORT STATIC RAM |
| 中文描述： | 4K X 16 DUAL-PORT SRAM, 35 ns, CPGA84 |
| 封裝： | 1.120 X 1.120 INCH, 0.160 INCH HEIGHT, CERAMIC, PGA-84 |
| 文件頁(yè)數(shù)： | 13/17頁(yè) |
| 文件大?。?/td> | 281K |
| 代理商： | IDT70V24S35G |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)當(dāng)前第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)
6.38
13
IDT70V24S/L
HIGH-SPEED 3.3V 4K x 16 DUAL-PORT STATIC RAM
COMMERCIAL TEMPERATURE RANGE
TRUTH TABLE IV —
ADDRESS BUSY ARBITRATION
Inputs
A
0L
-A
11L
CE
L
CE
R
A
0R
-A
11R
X
X
NO MATCH
H
X
MATCH
X
H
MATCH
L
L
MATCH
Outputs
BUSY
L(1)
H
H
H
(2)
BUSY
R(1)
H
H
H
(2)
Function
Normal
Normal
Normal
Write Inhibit
(3)
NOTES:
1. Pins
BUSY
L
and
BUSY
R
are both outputs when the part is configured as a master. Both are inputs when configured as a slave.
BUSY
outputs on the
IDT70V24 are push pull, not open drain outputs. On slaves the
BUSY
input internally inhibits writes.
2. L if the inputs to the opposite port were stable prior to the address and enable inputs of this port. H if the inputs to the opposite port became stable after
the address and enable inputs of this port. If t
APS
is not met, either
BUSY
L
or
BUSY
R
= Low will result.
BUSY
L
and
BUSY
R
outputs cannot be low
simultaneously.
3. Writes to the left port are internally ignored when
BUSY
L
outputs are driving low regardless of actual logic level on the pin. Writes to the right port are
internally ignored when
BUSY
R
outputs are driving low regardless of actual logic level on the pin.
2911 tbl 16
TRUTH TABLE V — EXAMPLE OF SEMAPHORE PROCUREMENT SEQUENCE
(1,2)
Functions
D
0
- D
15
Left
No Action
1
Left Port Writes "0" to Semaphore
0
Right Port Writes "0" to Semaphore
0
Left Port Writes "1" to Semaphore
1
Left Port Writes "0" to Semaphore
1
Right Port Writes "1" to Semaphore
0
Left Port Writes "1" to Semaphore
1
Right Port Writes "0" to Semaphore
1
Right Port Writes "1" to Semaphore
1
Left Port Writes "0" to Semaphore
0
Left Port Writes "1" to Semaphore
1
D
0
- D
15
Right
Status
1
1
1
0
0
1
1
0
1
1
1
Semaphore free
Left port has semaphore token
No change. Right side has no write access to semaphore
Right port obtains semaphore token
No change. Left port has no write access to semaphore
Left port obtains semaphore token
Semaphore free
Right port has semaphore token
Semaphore free
Right port has semaphore token
Semaphore free
NOTES:
1. This table denotes a sequence of events for only one of the eight semaphores on the IDT70V24.
2. There are eight semaphore flags written to via I/O
0
and read from all I/O's (I/O
0
-I/O
15
). These eight semaphores are addressed by A
0
- A
2
.
FUNCTIONAL DESCRIPTION
The IDT70V24 provides two ports with separate control,
address and I/O pins that permit independent access for reads
or writes to any location in memory. The IDT70V24 has an
automatic power down feature controlled by
CE
. The
CE
controls on-chip power down circuitry that permits the
respective port to go into a standby mode when not selected
(
CE
High). When a port is enabled, access to the entire
memory array is permitted.
2911 tbl 17
INTERRUPTS
If the user chooses to use the interrupt function, a memory
location (mail box or message center) is assigned to each port.
The left port interrupt flag (
INT
L
) is asserted when the right port
writes to memory location FFE (HEX), where a write is defined
as the
CE
=R/
W
=V
IL
per the Truthe Table. The left port clears
the interrupt by accessing address location FFE when
CE
R
=
OE
R
=V
IL
, R/
W
is a "don't care". Likewise, the right port
interrupt flag (
INT
R
) is asserted when the left port writes to
memory location FFF (HEX) and to clear the interrupt flag
(
INT
R
), the right port must read the memory location FFF. The
message (16 bits) at FFE or FFF is user-defined, since it is an
addressable SRAM location. If the interrupt function is not
used, address locations FFE and FFF are not used as mail
boxes, but as part of the random access memory. Refer to
Truth Table for the interrupt operation.
BUSY LOGIC
Busy Logic provides a hardware indication that both ports
of the RAM have accessed the same location at the same
time. It also allows one of the two accesses to proceed and
signals the other side that the RAM is “Busy”. The busy pin can
then be used to stall the access until the operation on the other
side is completed. If a write operation has been attempted
from the side that receives a busy indication, the write signal
is gated internally to prevent the write from proceeding.
The use of busy logic is not required or desirable for all
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| IDT70V24S35J | HIGH-SPEED 3.3V 4K x 16 DUAL-PORT STATIC RAM |
| IDT70V24S35PF | HIGH-SPEED 3.3V 4K x 16 DUAL-PORT STATIC RAM |
| IDT70V24L | HIGH-SPEED 3.3V 4K x 16 DUAL-PORT STATIC RAM |
| IDT70V24S | HIGH-SPEED 3.3V 4K x 16 DUAL-PORT STATIC RAM |
| IDT70V24S55G | HIGH-SPEED 3.3V 4K x 16 DUAL-PORT STATIC RAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IDT70V24S35J | 功能描述:IC SRAM 64KBIT 35NS 84PLCC RoHS:否 類別:集成電路 (IC) >> 存儲(chǔ)器 系列:- 標(biāo)準(zhǔn)包裝:45 系列:- 格式 - 存儲(chǔ)器:RAM 存儲(chǔ)器類型:SRAM - 雙端口，異步 存儲(chǔ)容量:128K（8K x 16） 速度:15ns 接口:并聯(lián) 電源電壓:3 V ~ 3.6 V 工作溫度:0°C ~ 70°C 封裝/外殼:100-LQFP 供應(yīng)商設(shè)備封裝:100-TQFP（14x14） 包裝:托盤 其它名稱:70V25S15PF |
| IDT70V24S35J8 | 功能描述:IC SRAM 64KBIT 35NS 84PLCC RoHS:否 類別:集成電路 (IC) >> 存儲(chǔ)器 系列:- 標(biāo)準(zhǔn)包裝:72 系列:- 格式 - 存儲(chǔ)器:RAM 存儲(chǔ)器類型:SRAM - 同步 存儲(chǔ)容量:9M（256K x 36） 速度:75ns 接口:并聯(lián) 電源電壓:3.135 V ~ 3.465 V 工作溫度:-40°C ~ 85°C 封裝/外殼:100-LQFP 供應(yīng)商設(shè)備封裝:100-TQFP（14x14） 包裝:托盤 其它名稱:71V67703S75PFGI |
| IDT70V24S35PF | 功能描述:IC SRAM 64KBIT 35NS 100TQFP RoHS:否 類別:集成電路 (IC) >> 存儲(chǔ)器 系列:- 標(biāo)準(zhǔn)包裝:45 系列:- 格式 - 存儲(chǔ)器:RAM 存儲(chǔ)器類型:SRAM - 雙端口，異步 存儲(chǔ)容量:128K（8K x 16） 速度:15ns 接口:并聯(lián) 電源電壓:3 V ~ 3.6 V 工作溫度:0°C ~ 70°C 封裝/外殼:100-LQFP 供應(yīng)商設(shè)備封裝:100-TQFP（14x14） 包裝:托盤 其它名稱:70V25S15PF |
| IDT70V24S35PF8 | 功能描述:IC SRAM 64KBIT 35NS 100TQFP RoHS:否 類別:集成電路 (IC) >> 存儲(chǔ)器 系列:- 標(biāo)準(zhǔn)包裝:72 系列:- 格式 - 存儲(chǔ)器:RAM 存儲(chǔ)器類型:SRAM - 同步 存儲(chǔ)容量:9M（256K x 36） 速度:75ns 接口:并聯(lián) 電源電壓:3.135 V ~ 3.465 V 工作溫度:-40°C ~ 85°C 封裝/外殼:100-LQFP 供應(yīng)商設(shè)備封裝:100-TQFP（14x14） 包裝:托盤 其它名稱:71V67703S75PFGI |
| IDT70V24S55G | 功能描述:IC SRAM 64KBIT 55NS 84PGA RoHS:否 類別:集成電路 (IC) >> 存儲(chǔ)器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:- 格式 - 存儲(chǔ)器:RAM 存儲(chǔ)器類型:SRAM - 雙端口，同步 存儲(chǔ)容量:1.125M（32K x 36） 速度:5ns 接口:并聯(lián) 電源電壓:3.15 V ~ 3.45 V 工作溫度:-40°C ~ 85°C 封裝/外殼:256-LBGA 供應(yīng)商設(shè)備封裝:256-CABGA（17x17） 包裝:帶卷 (TR) 其它名稱:70V3579S5BCI8 |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。