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參數(shù)資料
| 型號： | IDT70V25L15GI |
| 廠商： | Integrated Device Technology, Inc. |
| 英文描述： | HIGH-SPEED 3.3V 8K x 16 DUAL-PORT STATIC RAM |
| 中文描述： | 高速3.3 8K的× 16 DUAL-PORT靜態(tài)RAM |
| 文件頁數(shù)： | 19/22頁 |
| 文件大?。?/td> | 186K |
| 代理商： | IDT70V25L15GI |
6.42
IDT70V25S/L
High-Speed 8K x 16 Dual-Port Static RAM Industrial and Commercial Temperature Ranges
Figure 3. Busy and chip enable routing for both width and depth expansion with IDT70V25 SRAMs.
write operations can be prevented to a port by tying the
BUSY
pin for that
port LOW.
The
BUSY
outputs on the IDT 70V25 SRAMin master mode, are
push-pull type outputs and do not require pull up resistors to operate. If
these SRAMs are being expanded in depth, then the
BUSY
indication for
the resulting array requires the use of an external AND gate.
-+%9/<%1C
,.:1
When expanding an IDT70V25 SRAMarray in width while using
BUSY
logic, one master part is used to decide which side of the SRAM
array will receive a
BUSY
indication, and to output that indication. Any
number of slaves to be addressed in the same address range as the
master, use the
BUSY
signal as a write inhibit signal. Thus on the
IDT70V25 SRAMthe
BUSY
pin is an output if the part is used as a
master (M/
S
pin = V
IH
), and the
BUSY
pin is an input if the part used
as a slave (M/
S
pin = V
IL
) as shown in Figure 3.
If two or more master parts were used when expanding in width, a
split decision could result with one master indicating
BUSY
on one side
of the array and another master indicating
BUSY
on one other side of
the array. This would inhibit the write operations fromone port for part
of a word and inhibit the write operations fromthe other port for the
other part of the word.
The
BUSY
arbitration, on a master, is based on the chip enable and
address signals only. It ignores whether an access is a read or write.
In a master/slave array, both address and chip enable must be valid
long enough for a
BUSY
flag to be output fromthe master before the
actual write pulse can be initiated with either the R/
W
signal or the byte
enables. Failure to observe this timng can result in a glitched internal
write inhibit signal and corrupted data in the slave.
.%
The IDT70V25 is an extremely fast Dual-Port 8K x 16 CMOS Static
RAMwith an additional 8 address locations dedicated to binary
semaphore flags. These flags allow either processor on the left or right
side of the Dual-Port SRAMto claima privilege over the other
processor for functions defined by the systemdesigner
’
s software. As
an example, the semaphore can be used by one processor to inhibit
the other fromaccessing a portion of the Dual-Port SRAMor any other
The IDT70V25 provides two ports with separate control, address
and I/O pins that permt independent access for reads or writes to any
location in memory. The IDT70V25 has an automatic power down
feature controlled by
CE
. The
CE
controls on-chip power down circuitry
that permts the respective port to go into a standby mode when not
selected (
CE
HIGH). When a port is enabled, access to the entire
memory array is permtted.
'
If the user chooses the interrupt function, a memory location (mail
box or message center) is assigned to each port. The left port interrupt
flag (
INT
L
) is asserted when the right port writes to memory location
1FFE (HEX), where a write is defined as the
CE
R
= R/
W
R
= V
IL
per
Truth Table III. The left port clears the interrupt by an address location
1FFE access when
CE
L
=
OE
L
= V
IL
, R/
W
L
is a "don't care". Likewise,
the right port interrupt flag (
INT
R
) is set when the left port writes to
memory location 1FFF (HEX) and to clear the interrupt flag (
INT
R
), the
right port must read the memory location 1FFF. The message (16 bits)
at 1FFE or 1FFF is user-defined, since it is an addressable SRAM
location. If the interrupt function is not used, address locations 1FFE
and 1FFF are not used as mail boxes, but as part of the randomaccess
memory. Refer to Truth Table III for the interrupt operation.
1C
Busy Logic provides a hardware indication that both ports of the
SRAMhave accessed the same location at the same time. It also
allows one of the two accesses to proceed and signals the other side
that the SRAMis
“
busy
”
. The
BUSY
pin can then be used to stall the
access until the operation on the other side is completed. If a write
operation has been attempted fromthe side that receives a
BUSY
indication, the write signal is gated internally to prevent the write from
proceeding.
The use of
BUSY
logic is not required or desirable for all applica-
tions. In some cases it may be useful to logically OR the
BUSY
outputs
together and use any
BUSY
indication as an interrupt source to flag the
event of an illegal or illogical operation. If the write inhibit function of
BUSY
logic is not desirable, the
BUSY
logic can be disabled by placing
the part in slave mode with the M/
S
pin. Once in slave mode the
BUSY
pin operates solely as a write inhibit input pin. Normal operation can be
programmed by tying the
BUSY
pins HIGH. If desired, unintended
2944 drw 18
MASTER
Dual Port
SRAM
BUSY
L
BUSY
R
CE
MASTER
Dual Port
SRAM
BUSY
L
BUSY
R
CE
SLAVE
Dual Port
SRAM
BUSY
L
BUSY
R
CE
SLAVE
Dual Port
SRAM
BUSY
L
BUSY
R
CE
BUSY
L
BUSY
R
D
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| IDT70V25S15G | HIGH-SPEED 3.3V 8K x 16 DUAL-PORT STATIC RAM |
| IDT70V25S15GI | HIGH-SPEED 3.3V 8K x 16 DUAL-PORT STATIC RAM |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IDT70V25L15J | 功能描述:IC SRAM 128KBIT 15NS 84PLCC RoHS:否 類別:集成電路 (IC) >> 存儲器 系列:- 標準包裝:1,000 系列:- 格式 - 存儲器:RAM 存儲器類型:SRAM - 雙端口，同步 存儲容量:1.125M（32K x 36） 速度:5ns 接口:并聯(lián) 電源電壓:3.15 V ~ 3.45 V 工作溫度:-40°C ~ 85°C 封裝/外殼:256-LBGA 供應商設備封裝:256-CABGA（17x17） 包裝:帶卷 (TR) 其它名稱:70V3579S5BCI8 |
| IDT70V25L15J8 | 功能描述:IC SRAM 128KBIT 15NS 84PLCC RoHS:否 類別:集成電路 (IC) >> 存儲器 系列:- 標準包裝:45 系列:- 格式 - 存儲器:RAM 存儲器類型:SRAM - 雙端口，異步 存儲容量:128K（8K x 16） 速度:15ns 接口:并聯(lián) 電源電壓:3 V ~ 3.6 V 工作溫度:0°C ~ 70°C 封裝/外殼:100-LQFP 供應商設備封裝:100-TQFP（14x14） 包裝:托盤 其它名稱:70V25S15PF |
| IDT70V25L15PF | 功能描述:IC SRAM 128KBIT 15NS 100TQFP RoHS:否 類別:集成電路 (IC) >> 存儲器 系列:- 標準包裝:2,500 系列:- 格式 - 存儲器:EEPROMs - 串行 存儲器類型:EEPROM 存儲容量:1K (128 x 8) 速度:100kHz 接口:UNI/O?（單線） 電源電壓:1.8 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 封裝/外殼:8-TSSOP，8-MSOP（0.118"，3.00mm 寬） 供應商設備封裝:8-MSOP 包裝:帶卷 (TR) |
| IDT70V25L15PF8 | 功能描述:IC SRAM 128KBIT 15NS 100TQFP RoHS:否 類別:集成電路 (IC) >> 存儲器 系列:- 標準包裝:45 系列:- 格式 - 存儲器:RAM 存儲器類型:SRAM - 雙端口，異步 存儲容量:128K（8K x 16） 速度:15ns 接口:并聯(lián) 電源電壓:3 V ~ 3.6 V 工作溫度:0°C ~ 70°C 封裝/外殼:100-LQFP 供應商設備封裝:100-TQFP（14x14） 包裝:托盤 其它名稱:70V25S15PF |
| IDT70V25L15PFG | 功能描述:IC SRAM 128KBIT 15NS 100TQFP RoHS:是 類別:集成電路 (IC) >> 存儲器 系列:- 標準包裝:2,500 系列:- 格式 - 存儲器:EEPROMs - 串行 存儲器類型:EEPROM 存儲容量:1K (128 x 8) 速度:100kHz 接口:UNI/O?（單線） 電源電壓:1.8 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 封裝/外殼:8-TSSOP，8-MSOP（0.118"，3.00mm 寬） 供應商設備封裝:8-MSOP 包裝:帶卷 (TR) |
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