參數(shù)資料
型號(hào): IDT70V25L15J
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: DRAM
英文描述: HIGH-SPEED 3.3V 8K x 16 DUAL-PORT STATIC RAM
中文描述: 8K X 16 DUAL-PORT SRAM, 15 ns, PQCC84
封裝: 1.150 X 1.150 INCH, 0.170 INCH HEIGHT, PLASTIC, LCC-84
文件頁數(shù): 11/22頁
文件大?。?/td> 186K
代理商: IDT70V25L15J
6.42
IDT70V25S/L
High-Speed 8K x 16 Dual-Port Static RAM Industrial and Commercial Temperature Ranges
$-:-1!#*,
W
+$
5
NOTES:
1. R/
W
or
CE
or
UB
&
LB
must be HIGH during all address transitions.
2. A write occurs during the overlap (t
EW
or t
WP
) of a LOW
UB
or
LB
and a LOW
CE
and a LOW R/
W
for memory array writing cycle.
3. t
WR
is measured fromthe earlier of
CE
or R/
W
(or
SEM
or R/
W
) going HIGH to the end-of-write cycle.
4. During this period, the I/O pins are in the output state and input signals must not be applied.
5. If the
CE
or
SEM
LOW transition occurs simultaneously with or after the R/
W
LOW transition the outputs remain in the HIGH-impedance state.
6. Timng depends on which enable signal is asserted last,
CE
, R/
W
, or
UB
or
LB
.
7. This parameter is guaranteed by device characterization, but is not production tested. Transition is measured 0mV fromsteady state with Output Test Load
(Figure 2).
8. If
OE
is LOW during R/
W
controlled write cycle, the write pulse width must be the larger of t
WP
or (t
WZ
+ t
DW
) to allow the I/O drivers to turn off and data to be
placed on the bus for the required t
DW
. If
OE
is HIGH during an R/
W
controlled write cycle, this requirement does not apply and the write pulse can be as short as
the specified t
WP
.
9. To access SRAM
CE
= V
IL
,
UB
or
LB
=
V
IL
,
and
SEM
= V
IH
.
To access Semaphore,
CE
= V
IH
or
UB
and
LB
=
V
IH
,
and
SEM
= V
IL
.
t
EW
must be met for either condition.
$-:-1!#
CE UB LB
+$
5
R/
W
t
WC
t
HZ
t
AW
t
WR
t
AS
t
WP
DATA
OUT
(2)
t
WZ
t
DW
t
DH
t
OW
OE
ADDRESS
DATA
IN
(6)
(4)
(4)
(7)
CE
or
SEM
2944 drw 08
(9)
CE
or
SEM
(9)
(7)
(3)
2944 drw09
t
WC
t
AS
t
WR
t
DW
t
DH
ADDRESS
DATA
IN
R/
W
t
AW
t
EW
UB
or
LB
(3)
(2)
(6)
CE
or
SEM
(9)
(9)
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