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參數(shù)資料
| 型號： | IDT70V25L25PF |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | DRAM |
| 英文描述： | HIGH-SPEED 3.3V 8K x 16 DUAL-PORT STATIC RAM |
| 中文描述： | 8K X 16 DUAL-PORT SRAM, 25 ns, PQFP100 |
| 封裝： | 14 X 14 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100 |
| 文件頁數(shù)： | 16/17頁 |
| 文件大?。?/td> | 276K |
| 代理商： | IDT70V25L25PF |
6.39
16
IDT70V25S/L
HIGH-SPEED 3.3V 8K x 16 DUAL-PORT STATIC RAM
COMMERCIAL TEMPERATURE RANGE
be handled via the initialization program at power-up. Since
any semaphore request flag which contains a zero must be
reset to a one, all semaphores on both sides should have a
one written into them at initialization from both sides to assure
that they will be free when needed.
USING SEMAPHORES—SOME EXAMPLES
Perhaps the simplest application of semaphores is their
application as resource markers for the IDT70V25’s Dual-Port
RAM. Say the 8K x 16 RAM was to be divided into two 4K x 16
blocks which were to be dedicated at any one time to servicing
either the left or right port. Semaphore 0 could be used to
indicate the side which would control the lower section of
memory, and Semaphore 1 could be defined as the indicator
for the upper section of memory.
To take a resource, in this example the lower 4K of
Dual-Port RAM, the processor on the left port could write and
then read a zero in to Semaphore 0. If this task were success-
fully completed (a zero was read back rather than a one), the
left processor would assume control of the lower 4K. Mean-
while the right processor was attempting to gain control of the
resource after the left processor, it would read back a one in
response to the zero it had attempted to write into Semaphore
0. At this point, the software could choose to try and gain
control of the second 4K section by writing, then reading a zero
into Semaphore 1. If it succeeded in gaining control, it would
lock out the left side.
Once the left side was finished with its task, it would write
a one to Semaphore 0 and may then try to gain access to
Semaphore 1. If Semaphore 1 was still occupied by the right
side, the left side could undo its semaphore request and
perform other tasks until it was able to write, then read a zero
into Semaphore 1. If the right processor performs a similar
task with Semaphore 0, this protocol would allow the two
processors to swap 4K blocks of Dual-Port RAM with each
other.
The blocks do not have to be any particular size and can
even be variable, depending upon the complexity of the
software using the semaphore flags. All eight semaphores
could be used to divide the Dual-Port RAM or other shared
resources into eight parts. Semaphores can even be assigned
different meanings on different sides rather than being given
a common meaning as was shown in the example above.
Semaphores are a useful form of arbitration in systems like
disk interfaces where the CPU must be locked out of a section
of memory during a transfer and the I/O device cannot tolerate
any wait states. With the use of semaphores, once the two
devices has determined which memory area was “off-limits” to
the CPU, both the CPU and the I/O devices could access their
assigned portions of memory continuously without any wait
states.
Semaphores are also useful in applications where no
memory “WAIT” state is available on one or both sides. Once
a semaphore handshake has been performed, both proces-
sors can access their assigned RAM segments at full speed.
Another application is in the area of complex data struc-
tures. In this case, block arbitration is very important. For this
application one processor may be responsible for building and
updating a data structure. The other processor then reads
and interprets that data structure. If the interpreting processor
reads an incomplete data structure, a major error condition
may exist. Therefore, some sort of arbitration must be used
between the two different processors. The building processor
arbitrates for the block, locks it and then is able to go in and
update the data structure. When the update is completed, the
data structure block is released. This allows the interpreting
processor to come back and read the complete data structure,
thereby guaranteeing a consistent data structure.
Figure 4. IDT70V25 Semaphore Logic
D
2944 drw 19
0
D
Q
WRITE
D
0
WRITE
D
Q
SEMAPHORE
REQUEST FLIP FLOP
SEMAPHORE
REQUEST FLIP FLOP
L PORT
R PORT
SEMAPHORE
READ
SEMAPHORE
READ
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| IDT70V25L | HIGH-SPEED 3.3V 8K x 16 DUAL-PORT STATIC RAM |
| IDT70V25S | HIGH-SPEED 3.3V 8K x 16 DUAL-PORT STATIC RAM |
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| IDT70V25S55J | HIGH-SPEED 3.3V 8K x 16 DUAL-PORT STATIC RAM |
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| IDT70V25L25PF8 | 功能描述:IC SRAM 128KBIT 25NS 100TQFP RoHS:否 類別:集成電路 (IC) >> 存儲器 系列:- 標準包裝:45 系列:- 格式 - 存儲器:RAM 存儲器類型:SRAM - 雙端口，異步 存儲容量:128K（8K x 16） 速度:15ns 接口:并聯(lián) 電源電壓:3 V ~ 3.6 V 工作溫度:0°C ~ 70°C 封裝/外殼:100-LQFP 供應(yīng)商設(shè)備封裝:100-TQFP（14x14） 包裝:托盤 其它名稱:70V25S15PF |
| IDT70V25L25PFGI | 功能描述:IC SRAM 128KBIT 25NS 100TQFP RoHS:是 類別:集成電路 (IC) >> 存儲器 系列:- 標準包裝:3,000 系列:- 格式 - 存儲器:EEPROMs - 串行 存儲器類型:EEPROM 存儲容量:32K (4K x 8) 速度:100kHz，400kHz 接口:I²C，2 線串口 電源電壓:2.5 V ~ 5.5 V 工作溫度:-40°C ~ 125°C 封裝/外殼:8-SOIC（0.154"，3.90mm 寬） 供應(yīng)商設(shè)備封裝:8-SOIC 包裝:帶卷 (TR) 其它名稱:CAV24C32WE-GT3OSTR |
| IDT70V25L25PFGI8 | 功能描述:IC SRAM 128KBIT 25NS 100TQFP RoHS:是 類別:集成電路 (IC) >> 存儲器 系列:- 標準包裝:45 系列:- 格式 - 存儲器:RAM 存儲器類型:SRAM - 雙端口，異步 存儲容量:128K（8K x 16） 速度:15ns 接口:并聯(lián) 電源電壓:3 V ~ 3.6 V 工作溫度:0°C ~ 70°C 封裝/外殼:100-LQFP 供應(yīng)商設(shè)備封裝:100-TQFP（14x14） 包裝:托盤 其它名稱:70V25S15PF |
| IDT70V25L25PFI | 功能描述:IC SRAM 128KBIT 25NS 100TQFP RoHS:否 類別:集成電路 (IC) >> 存儲器 系列:- 標準包裝:2,500 系列:- 格式 - 存儲器:EEPROMs - 串行 存儲器類型:EEPROM 存儲容量:1K (128 x 8) 速度:100kHz 接口:UNI/O?（單線） 電源電壓:1.8 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 封裝/外殼:8-TSSOP，8-MSOP（0.118"，3.00mm 寬） 供應(yīng)商設(shè)備封裝:8-MSOP 包裝:帶卷 (TR) |
| IDT70V25L25PFI8 | 功能描述:IC SRAM 128KBIT 25NS 100TQFP RoHS:否 類別:集成電路 (IC) >> 存儲器 系列:- 標準包裝:45 系列:- 格式 - 存儲器:RAM 存儲器類型:SRAM - 雙端口，異步 存儲容量:128K（8K x 16） 速度:15ns 接口:并聯(lián) 電源電壓:3 V ~ 3.6 V 工作溫度:0°C ~ 70°C 封裝/外殼:100-LQFP 供應(yīng)商設(shè)備封裝:100-TQFP（14x14） 包裝:托盤 其它名稱:70V25S15PF |
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